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1. 发明申请

WO2018017946A1 INSULATED GATE TURN-OFF DEVICE WITH TURN-OFF SCHOTTKY-BARRIER MOSFET 审中-公开
标题翻译：具有关断肖特基势垒MOSFET的绝缘栅极关断装置
公开(公告)号：WO2018017946A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/043269
申请日：2017-07-21
申请人： PAKAL TECHNOLOGIES LLC
发明人： BLANCHARD, Richard A. , RODOV, Vladimir , AKIYAMA, Hidenori , TWORZYDLO, Woytek
IPC分类号： H01L29/745 , H01L29/08 , H01L29/47 , H01L29/45
CPC分类号： H01L29/7396 , H01L27/0716 , H01L29/083 , H01L29/0839 , H01L29/105 , H01L29/456 , H01L29/47 , H01L29/7455 , H01L29/7813 , H01L29/7839
摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n- epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.
摘要翻译：形成为管芯的绝缘栅极关断（IGTO）器件具有包括p +层（例如，衬底），n-epi层，p阱等的分层结构。形成在p阱中的垂直绝缘栅电极和栅电极之间的n +区，从而形成垂直的npn和pnp晶体管。该设备由单元矩阵组成。要打开设备，以阴极为参考，将正电压施加到栅电极。单元还包含垂直p沟道MOSFET，用于将npn晶体管的基极与其发射极短路，当p沟道MOSFET由施加到栅极的轻微负电压导通时关断npn晶体管。 p沟道MOSFET包括在npn晶体管发射极的顶部表面形成的肖特基源极。

2. 发明申请

WO2016064702A1 SEMICONDUCTOR STRUCTURE WITH ACTIVE DEVICE AND DAMAGED REGION 审中-公开
标题翻译：具有主动装置和损坏区域的半导体结构
公开(公告)号：WO2016064702A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/056151
申请日：2015-10-19
申请人： SILANNA SEMICONDUCTOR U.S.A., INC.
发明人： NYGAARD, Paul, A. , STUBER, Michael, A.
IPC分类号： H01L29/786
CPC分类号： H01L27/1203 , H01L21/265 , H01L21/32053 , H01L21/84 , H01L27/0629 , H01L29/1095 , H01L29/32 , H01L29/47 , H01L29/66143 , H01L29/66477 , H01L29/7839 , H01L29/78612 , H01L29/872
摘要： A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.
摘要翻译：半导体结构形成有具有活性器件的有源层，其包括体区。有源器件通过在半导体绝缘体晶片的顶侧中和顶侧处理形成。通过在半导体绝缘体晶片的底侧处的底侧处理，在体区域的一部分内形成受损区域，该受损区域具有足以防止在有源器件的操作中的扭结效应和自锁存的结构。

3. 发明申请

WO2013095349A1 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有金属源和漏区的半导体器件
公开(公告)号：WO2013095349A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/065931
申请日：2011-12-19
申请人： INTEL CORPORATION , GILES, Martin, D. , CAPPELLANI, Annalisa , KABEHIE, Sanaz , RIOS, Rafael , WEBER, Cory, E. , BUDREVICH, Aaron A.
发明人： GILES, Martin, D. , CAPPELLANI, Annalisa , KABEHIE, Sanaz , RIOS, Rafael , WEBER, Cory, E. , BUDREVICH, Aaron A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

4. 发明申请

WO2013000196A1 一种半导体结构及其制造方法审中-公开
公开(公告)号：WO2013000196A1
公开(公告)日：2013-01-03
申请号：PCT/CN2011/078877
申请日：2011-08-25
申请人：中国科学院微电子研究所 , 北京北方微电子基地设备工艺研究中心有限责任公司 , 尹海洲 , 朱慧珑 , 骆志炯
发明人：尹海洲 , 朱慧珑 , 骆志炯
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28008 , H01L29/41733 , H01L29/4232 , H01L29/66545 , H01L29/66643 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要：本发明提供了一种半导体结构的制造方法，该方法包括：提供SOI衬底，并在所述SOI衬底上形成栅极结构；刻蚀所述栅极结构两侧的所述SOI衬底的SOI层和BOX层，以形成暴露所述BOX层的沟槽，该沟槽部分进入所述BOX层；在所述沟槽的侧壁形成侧墙；在所述沟槽内形成覆盖所述侧墙的金属层，该金属层与所述栅极结构下方的所述SOI层相接触。相应地，本发明还提供一种使用上述方法形成的半导体结构。本发明提供的制造方法和半导体结构使得半导体器件在工作时金属层与SOI衬底的体硅层之间的电容减小，有利于提升半导体器件的性能。

5. 发明申请

WO2011088735A1 一种混合结型源漏场效应晶体管及其制备方法审中-公开
公开(公告)号：WO2011088735A1
公开(公告)日：2011-07-28
申请号：PCT/CN2011/000013
申请日：2011-01-04
申请人：复旦大学 , 吴东平 , 张世理 , 葛亮 , 仇志军
发明人：吴东平 , 张世理 , 葛亮 , 仇志军
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66643 , H01L29/7839

6. 发明申请

WO2007060641A1 METHOD OF FABRICATING SELF ALIGNED SCHOTTKY JUNCTIONS FOR SEMICONDUCTORS DEVICES 审中-公开
标题翻译：用于半导体器件的自对准肖特基结的方法
公开(公告)号：WO2007060641A1
公开(公告)日：2007-05-31
申请号：PCT/IB2006/054446
申请日：2006-11-27
申请人： NXP B.V. , MULLER, Markus
发明人： MULLER, Markus
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/66636 , H01L29/66643 , H01L29/7839
摘要： A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self- aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well contolled.
摘要翻译：一种制造相对于半导体器件的自对准肖特基结（29）的方法。在栅极蚀刻和间隔物形成之后，在硅衬底（10）中形成限定结区的凹槽，并且选择性地生长SiGe层（22）。然后在栅极（14）和SiGe层（22）之上提供介电层（24），进行接触蚀刻以形成接触孔（26），然后去除SiGe材料（22）以产生空腔（28 ）在连接区域。最后，用金属填充空腔（28）以形成结（29）。因此，提供了一种用于自对准制造具有相对低电阻率的肖特基结的工艺，其中结的形状和位置可以很好地形成。

7. 发明申请

WO2006105052A1 SCHOTTKY BARRIER MOSFET DEVICE AND CIRCUIT 审中-公开
标题翻译：肖特基栅极MOSFET器件和电路
公开(公告)号：WO2006105052A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011207
申请日：2006-03-24
申请人： SPINNAKER SEMICONDUCTOR, INC , LARSON, John, M. , SNYDER, John, P.
发明人： LARSON, John, M. , SNYDER, John, P.
IPC分类号： H01L29/78
CPC分类号： H01L21/823814 , H01L27/095 , H01L29/66643 , H01L29/7839
摘要： A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a lower capacitance between source and gate, which improves device and circuit power and speed performance.
摘要翻译：公开了一种肖特基势垒集成电路，该电路具有至少一个PMOS器件或至少一个NMOS器件，PMOS器件或NMOS器件中的至少一个具有金属源极 - 漏极接触，形成肖特基势垒或肖特基接触到半导体基质。该器件在源极和栅极之间提供较低的电容，从而提高器件和电路的功率和速度性能。

8. 发明申请

WO2006020043A1 METAL SOURCE POWER TRANSISTOR AND METHOD OF MANUFACTURE 审中-公开
标题翻译：金属源功率晶体管及其制造方法
公开(公告)号：WO2006020043A1
公开(公告)日：2006-02-23
申请号：PCT/US2005/025187
申请日：2005-07-15
申请人： SPINNAKER SEMICONDUCTOR, INC. , SNYDER, John, P.
发明人： SNYDER, John, P.
IPC分类号： H01L29/78 , H01L29/739
CPC分类号： H01L29/7802 , H01L29/0839 , H01L29/1083 , H01L29/41741 , H01L29/66643 , H01L29/7397 , H01L29/7813 , H01L29/7839 , H01L29/872
摘要： A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source made of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up are avoided, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.
摘要翻译：提供了一种金属源功率晶体管器件及其制造方法，其中金属源功率晶体管具有由金属制成的源并且与晶体管的体区和沟道区形成肖特基势垒。金属源功率晶体管无条件地免受寄生双极性作用，因此避免了卡扣和闩锁的影响，而不需要接触身体。允许身体漂浮在金属源功率晶体管中的能力降低了工艺复杂性，并允许更紧凑的器件布局。

9. 发明申请

WO2005069379A3 METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS 审中-公开
标题翻译：用于识别电气连接处的半导体的FERMI电平的方法和包含这种结点的器件
公开(公告)号：WO2005069379A3
公开(公告)日：2005-10-13
申请号：PCT/US2004042084
申请日：2004-12-14
申请人： ACORN TECH INC , GRUPP DANIEL E , CONNELLY DANIEL J
发明人： GRUPP DANIEL E , CONNELLY DANIEL J
IPC分类号： H01L21/285 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/47 , H01L29/78 , H01L29/786 , H01L29/812 , H01L29/872
CPC分类号： H01L29/0895 , H01L21/28537 , H01L29/45 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66636 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/812
摘要： An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 ohm-µm , and in some cases a minimum specific contact resistance.
摘要翻译：包括半导体（例如，C，Ge或Si基半导体），导体和设置在其间的界面层的电连接。界面层足够厚以消除半导体的费米能级，但足够薄以提供具有小于或等于约1000欧姆 - 米2的特定接触电阻的结，并且在一些情况下为最小特定接触抵抗性。

10. 发明申请

WO2005069379A2 METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS 审中-公开
标题翻译：用于在电学接合处确定半导体的铁磁性水平的方法以及包含这种接合的器件
公开(公告)号：WO2005069379A2
公开(公告)日：2005-07-28
申请号：PCT/US2004/042084
申请日：2004-12-14
申请人： ACORN TECHNOLOGIES, INC. , GRUPP, Daniel, E. , CONNELLY, Daniel, J.
发明人： GRUPP, Daniel, E. , CONNELLY, Daniel, J.
IPC分类号： H01L29/47
CPC分类号： H01L29/0895 , H01L21/28537 , H01L29/45 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66636 , H01L29/78 , H01L29/7827 , H01L29/7839 , H01L29/785 , H01L29/812
摘要： An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-µm 2 , and in some cases a minimum specific contact resistance.
摘要翻译：包括半导体（例如，C，Ge或Si基半导体）的电结，导体以及设置在其间的界面层。界面层足够厚，以便抑制半导体的费米能级，但又足够薄以提供具有小于或等于约1000Ω·m 2·m 2的特定接触电阻的结，以及在某些情况下，最小的特定接触电阻。

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