专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2020068322A1 SAVE-RESTORE CIRCUITRY WITH METAL-FERROELECTRIC-METAL DEVICES 审中-公开
公开(公告)号：WO2020068322A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/047768
申请日：2019-08-22
申请人： INTEL CORPORATION
发明人： VAIDYANATHAN, Kaushik , MORRIS, Daniel H. , LIU, Huichu , KURIAN, Dileep J. , AVCI, Uygar E. , KARNIK, Tanay , YOUNG, Ian A.
IPC分类号： G11C11/22 , G06F1/32 , G11C11/413
摘要： Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

2. 发明申请

WO2019022898A1 CONFIGURABLE INTERCONNECT APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2019022898A1
公开(公告)日：2019-01-31
申请号：PCT/US2018/039537
申请日：2018-06-26
申请人： INTEL CORPORATION
发明人： VAIDYANATHAN, Kaushik , MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A. , KARNIK, Tanay , LIU, Huichu
IPC分类号： G06F1/26 , H03K19/094
CPC分类号： G06F9/445 , G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/4411 , H03K19/018585
摘要： Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

3. 发明申请

WO2018194544A1 MULTI-BIT FERROELECTRIC MEMORY 审中-公开
公开(公告)号：WO2018194544A1
公开(公告)日：2018-10-25
申请号：PCT/US2017/027939
申请日：2017-04-17
申请人： INTEL CORPORATION
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/5657 , G11C11/22 , G11C11/221 , G11C11/223 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L27/1159 , H01L28/55 , H01L28/86 , H01L28/90 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： Embodiments are generally directed to a multi-bit ferroelectric memory. An embodiment of a multi-bit memory device includes a transistor element; and multiple ferroelectric material portions coupled to or integrated with a terminal of the transistor element, the ferroelectric material portions including at least a first ferroelectric material portion having a first polarization voltage, and a second ferroelectric material portion having a second polarization voltage, the second polarization voltage being different than the first polarization voltage.

4. 发明申请

WO2018063315A1 TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EMPLOYING CONTACT RESISTANCE REDUCING LAYER 审中-公开
标题翻译：隧道晶体管，包括源/漏区，使用接触电阻降低层
公开(公告)号：WO2018063315A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054732
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , YOUNG, Ian A. , AVCI, Uygar E.
IPC分类号： H01L29/78 , H01L29/73 , H01L29/66 , H01L21/8238 , H01L29/423
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823481 , H01L29/165 , H01L29/205 , H01L29/66795 , H01L29/7391 , H01L29/7851
摘要： Techniques are disclosed for forming tunneling transistors including source and drain (S/D) regions employing a contact resistance reducing layer. The contact resistance reducing layer may be formed between at least one of the S/D regions and its corresponding contact to improve the transistor performance. In addition, in some cases, material bandgap engineering may be used to enhance the ability of tunneling transistor devices, such as tunnel field-effect transistors (TFETs) and Fermi filter FETs (FFFETs), to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. Such material bandgap engineering can incorporate a material-based band offset component by using different material in the S/D regions to control off-state leakage, to expand upon the limited energy band offset achievable using single-composition material configurations. Increasing the band offset can increase the barrier that carriers must overcome to reach the channel region, thereby reducing off-state leakage.
摘要翻译：公开了用于形成包括采用接触电阻降低层的源极和漏极（S / D）区域的隧穿晶体管的技术。接触电阻降低层可以形成在S / D区域中的至少一个与其相应的接触之间以改善晶体管性能。另外，在一些情况下，可以使用材料带隙工程来增强诸如隧道场效应晶体管（TFET）和费米滤波器FET（FFFET）之类的隧道晶体管器件的能力以抵抗来自源的截止状态漏电流到漏极（通过通道）和从源极到地/基板。这种材料带隙工程可以通过使用S / D区域中的不同材料来控制截止状态泄漏，从而在使用单组分材料构造可实现的有限能带偏移时扩展基于材料的带偏移分量。增加频带偏移可以增加载波必须克服的到达信道区域的屏障，从而减少关闭状态泄漏。

5. 发明申请

WO2017052621A1 MEMORY CELL WITH ASYMMETRIC CONDUCTION TO REDUCE WRITE MINIMUM OPERATING VOLTAGE (WVMIN) AND POWER CONSUMPTION 审中-公开
标题翻译：具有不对称导通的存储器单元以减少写入最小工作电压（WVMIN）和功耗
公开(公告)号：WO2017052621A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052352
申请日：2015-09-25
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C7/02 , G11C11/412 , G11C11/419
摘要： Techniques for providing asymmetric conduction within an SRAM bit cell are provided and may substantially reduce energy consumption during write operations, and may also reduce the write minimum operation voltage (WVmin) for an SRAM device. In particular, some aspects disclosed herein include modifying or otherwise providing pull-up transistors configured to asymmetrically conduct to prevent current flow in a reverse direction, and more particularly, to prevent or otherwise mitigate current flowing back to Vcc during write operations. This can reduce voltage swings that would otherwise occur as internal bit cell nodes Q/Q# discharge, and thus, may reduce overall power consumption. The asymmetrical conducting characteristics may further reduce the magnitude of disturb currents within unselected cells (e.g., cells not selected for writes) and thus prevent the loss of data through inadvertent writes.
摘要翻译：提供了用于在SRAM位单元内提供不对称传导的技术，并且可以显着降低写入操作期间的能量消耗，并且还可以降低SRAM器件的写入最小工作电压（WVmin）。特别地，本文公开的一些方面包括修改或以其他方式提供被配置为不对称地导通的上拉晶体管，以防止在相反方向上的电流流动，更具体地，涉及防止或以其它方式缓解在写入操作期间流向Vcc的电流。这可以减少当内部位单元节点Q / Q＃放电时会发生的电压摆幅，从而可能降低总功耗。不对称导电特性可以进一步减小未选择的单元（例如，未被选择用于写入的单元）内的干扰电流的大小，从而通过无意写入来防止数据丢失。

6. 发明申请

WO2017044127A1 TRANSISTOR WITH DYNAMIC THRESHOLD VOLTAGE FOR LOW-LEAKAGE STANDBY AND HIGH SPEED ACTIVE MODE 审中-公开
标题翻译：具有低泄漏待机和高速激活模式的动态阈值电压的晶体管
公开(公告)号：WO2017044127A1
公开(公告)日：2017-03-16
申请号：PCT/US2015/049759
申请日：2015-09-11
申请人： INTEL CORPORATION
发明人： AVCI, Uygar E. , MORRIS, Daniel H. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78391 , H01L29/4908
摘要： Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.
摘要翻译：描述了一种装置，其包括：晶体管，包括：铁电材料层; 一层绝缘材料; 以及夹在铁电体层和绝缘材料层之间的氧化物层或金属层，其中铁电体材料的厚度小于绝缘材料层的厚度; 以及耦合到晶体管的驱动器。描述了一种装置，其包括：晶体管，包括：高K材料的第一氧化物层; 第二氧化物层; 以及夹在第一和第二氧化物层之间的纳米晶体层，其中第一氧化物层的厚度大于第二氧化物层的厚度; 以及耦合到晶体管的驱动器。

7. 发明申请

WO2015147838A1 P-TUNNELING FIELD EFFECT TRANSISTOR DEVICE WITH POCKET 审中-公开
标题翻译： P-TUNNELING场效应晶体管器件与POCKET
公开(公告)号：WO2015147838A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032059
申请日：2014-03-27
申请人： INTEL CORPORATION
发明人： AVCI, Uygar E. , KOTLYAR, Roza , YOUNG, Ian A.
IPC分类号： H01L29/88 , H01L29/78 , H01L21/18
CPC分类号： H01L29/66977 , G06F3/041 , H01L21/18 , H01L23/66 , H01L29/165 , H01L29/205 , H01L29/42312 , H01L29/66356 , H01L29/66742 , H01L29/7391 , H01L29/78 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L29/88 , H01L2223/6677
摘要： Described is a tunneling field effect transistor (TFET), comprising: a drain region having a first conductivity type; a source region having a second conductivity type opposite of the first conductivity type; a gate region to cause formation of a channel region between the source and drain regions; and a pocket disposed near a junction of the source region, wherein the pocket region formed from a material having lower percentage of one type of atom than percentage of the one type of atom in the source, channel, and drain regions.
摘要翻译：描述了隧道场效应晶体管（TFET），其包括：具有第一导电类型的漏极区; 源区域，具有与第一导电类型相反的第二导电类型; 栅极区域，用于在源区和漏区之间形成沟道区; 以及设置在所述源极区域的接合点附近的口袋，其中所述口袋区域由具有比所述源极，沟道和漏极区域中的一种类型的原子的百分比低的一种类型的原子的比例低的材料形成。

8. 发明申请

WO2019066875A1 FIELD EFFECT TRANSISTORS HAVING FERROELECTRIC OR ANTIFERROELECTRIC GATE DIELECTRIC STRUCTURE 审中-公开
公开(公告)号：WO2019066875A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054164
申请日：2017-09-28
申请人： INTEL CORPORATION , KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
发明人： KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51
摘要： Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

9. 发明申请

WO2019005089A1 FERROELECTRIC CHARGE PUMP 审中-公开
公开(公告)号：WO2019005089A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/040184
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： LIU, Huichu , MANIPATRUNI, Sasikanth , YOUNG, Ian A. , KARNIK, Tanay , MORRIS, Daniel H. , VAIDYANATHAN, Kaushik , AVCI, Uygar E. , NIKONOV, Dmitri E.
IPC分类号： H01L49/02
CPC分类号： H02M3/073
摘要： There is disclosed in one example a charge pump, including: a clock signal; an inverse clock signal; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

10. 发明申请

WO2017171860A1 TRANSISTOR THRESHOLD VOLTAGE VARIATION OPTIMIZATION 审中-公开
标题翻译：晶体管阈值电压变化优化
公开(公告)号：WO2017171860A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025663
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L27/04
CPC分类号： H01L27/088 , H01L21/823437 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/78
摘要： One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.
摘要翻译：一个实施例提供了一种装置。该装置包括第一晶体管和第二晶体管。第一晶体管包括第一漏极，通过第一沟道耦合到第一漏极的第一源极以及包括多个层的第一栅极堆叠。第二晶体管包括第二漏极，通过第二沟道耦合到第二漏极的第二源极以及包括多个层的第二栅极堆叠。每个栅极叠层包括功函数材料层以优化晶体管之间的阈值电压变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式