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1. 发明申请

WO2015142199A3 IMPROVED COOKED DOUGH FOR BAKED GOODS SUITABLE FOR BEING DEFROSTED 审中-公开
标题翻译：改进的烤面包适用于烘焙食品
公开(公告)号：WO2015142199A3
公开(公告)日：2015-12-10
申请号：PCT/PE2015000001
申请日：2015-02-09
申请人： SANCHEZ RIOS RAFAEL , HERRERA SERGIO DAVID
发明人： HERRERA SERGIO DAVID
IPC分类号： A21D10/00 , A21D8/00
CPC分类号： A21D13/0061 , A21D2/38 , A21D6/001 , A21D13/0009 , A21D13/16 , A21D13/24
摘要： The invention relates to a method and a product which, using conventional and basic systems and without the need for a particular system for defrosting and fermentation, achieves a optimum-quality product so that the consumer can determine whether same is fresh or originates from a defrosting process. In this way, a bread dough is achieved which is suitable for producing croissant-type products and all types of bread, of different shapes and sizes, and the post-baking quality of which is entirely favourable in terms of flavour, texture, appearance and volume, these characteristics not being altered after defrosting.
摘要翻译：本发明涉及一种使用常规和基本系统且不需要特定系统进行解冻和发酵的方法和产品，从而实现最佳质量的产品，使得消费者可以确定其是否是新鲜的还是源自解冻处理。通过这种方式，可以实现适用于生产具有不同形状和尺寸的羊角面包型产品和所有类型的面包的面包生面团，并且其后烘烤质量在风味，质地，外观和方面完全有利体积，这些特性在除霜后不会改变。

2. 发明申请

WO2015142199A2 MASA COCIDA MEJORADA PARA PANIFICADOS APTA PARA SU DESCONGELAMIENTO 审中-公开
标题翻译：改进适用于已经被破坏的商品
公开(公告)号：WO2015142199A2
公开(公告)日：2015-09-24
申请号：PCT/PE2015/000001
申请日：2015-02-09
申请人： SANCHEZ RIOS, Rafael , HERRERA, Sergio David
发明人： HERRERA, Sergio David
IPC分类号： A21D2/18
CPC分类号： A21D13/0061 , A21D2/38 , A21D6/001 , A21D13/0009 , A21D13/16 , A21D13/24
摘要： La presente invención trata de desarrollar un procedimiento y un producto que utilizando instalaciones básicas y comunmente empleadas y sin requerir una instalación especial para descongelación y fermentación, logra un producto de calidad óptima si que el consumidor pueda distinguir si el mismo es fresco o procede de un proceso de descongelamiento. Es asi que se consigue una masa de pan aplicable a la fabricación de medialunas, vigilantes y todo tipo de pan, con diversas formas y tamaños, y que posee cualidad de post-horneado totalmente favorables en cuanto a sabor, textura, aspecto, voluminosidad, las cuales no son alteradas después de su descongelado.
摘要翻译：本发明涉及一种方法和产品，其使用常规和基本系统，并且不需要用于除霜和发酵的特定系统，实现最优质量的产品，使得消费者可以确定其是否是新鲜的还是源自除霜处理。以这种方式，可以获得适合于生产不同形状和尺寸的羊角面包类产品和各种面包的面包面团，其后烘烤质量在风味，质地，外观和味道上都是完全有利的体积，这些特性在除霜后不会改变。

3. 发明申请

WO2013095650A1 NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有非离散源和排水区的纳米结构
公开(公告)号：WO2013095650A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067232
申请日：2011-12-23
申请人： INTEL CORPORATION , CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
发明人： CEA, Stephen M. , CAPPELLANI, Annalisa , GILES, Martin D. , RIOS, Rafael , KIM, Seiyon , KUHN, Kelin J.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78618 , B82Y40/00 , H01L21/268 , H01L29/0673 , H01L29/0847 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66742 , H01L29/66787 , H01L29/66977 , H01L29/7839 , H01L29/7845 , H01L29/7848 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
摘要翻译：描述了具有非离散源极和漏极区域的纳米线结构。例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。每个纳米线包括设置在纳米线中的离散通道区域。栅电极堆叠围绕多个垂直堆叠的纳米线。一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

4. 发明申请

WO2013095646A1 CMOS NANOWIRE STRUCTURE 审中-公开
标题翻译： CMOS纳米结构
公开(公告)号：WO2013095646A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067225
申请日：2011-12-23
申请人： INTEL CORPORATION , KIM, Seiyon , KUHN, Kelin, J. , GHANI, Tahir , MURTHY, Anand, S. , CAPPELLANI, Annalisa , CEA, Stephen, M. , RIOS, Rafael , GLASS, Glenn, A.
发明人： KIM, Seiyon , KUHN, Kelin, J. , GHANI, Tahir , MURTHY, Anand, S. , CAPPELLANI, Annalisa , CEA, Stephen, M. , RIOS, Rafael , GLASS, Glenn, A.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

5. 发明申请

WO2012074872A3 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 审中-公开
标题翻译：硅和硅锗纳米结构
公开(公告)号：WO2012074872A3
公开(公告)日：2012-10-04
申请号：PCT/US2011062059
申请日：2011-11-23
申请人： INTEL CORP , KUHN KELIN J , KIM SEIYON , RIOS RAFAEL , CEA STEPHEN M , GILES MARTIN D , CAPPELLANI ANNALISA , RAKSHIT TITASH , CHANG PETER , RACHMADY WILLY
发明人： KUHN KELIN J , KIM SEIYON , RIOS RAFAEL , CEA STEPHEN M , GILES MARTIN D , CAPPELLANI ANNALISA , RAKSHIT TITASH , CHANG PETER , RACHMADY WILLY
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

6. 发明申请

WO2017111798A1 HIGH RETENTION TIME MEMORY ELEMENT WITH DUAL GATE DEVICES 审中-公开
标题翻译：具有双栅极器件的高保留时间存储元件
公开(公告)号：WO2017111798A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000322
申请日：2015-12-23
申请人： INTEL CORPORATION , RIOS, Rafael , DEWEY, Gilbert , LE, Van, H. , METERELLIYOZ, Mesut
发明人： RIOS, Rafael , DEWEY, Gilbert , LE, Van, H. , METERELLIYOZ, Mesut , KAVALIEROS, Jack
IPC分类号： G11C11/409 , G11C11/4097
CPC分类号： G11C11/409 , G11C8/14 , G11C11/404 , G11C11/405 , G11C11/4097 , G11C2211/4068
摘要： A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.
摘要翻译：描述具有双栅极器件的高保留时间存储器元件。在一个示例中，存储器元件具有写入晶体管，该写入晶体管具有金属栅极，该金属栅极具有耦合到写入位线的源极，耦合到写入线的栅极和耦合到存储节点的漏极，其中值被写入存储器通过启动栅极并将该值施加到位线来实现节点，以及具有耦合到读取线的源极，耦合到存储节点的栅极和耦合到读取位线的漏极的读取晶体管，其中，通过将电流施加到源并读取感测线来确定栅极的状态来感测存储节点。

7. 发明申请

WO2016007135A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
标题翻译：基于负面差分电阻的记忆
公开(公告)号：WO2016007135A1
公开(公告)日：2016-01-14
申请号：PCT/US2014/045695
申请日：2014-07-08
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.
摘要翻译：描述了一种存储位单元，包括：存储节点; 耦合到存储节点的存取晶体管; 电容器，其具有耦合到所述存储节点的第一端子; 以及耦合到存储节点的一个或多个负差分电阻器件，使得存储位单元不具有接地线或供电线之一或两者。

8. 发明申请

WO2014142910A1 NANOWIRE-BASED MECHANICAL SWITCHING DEVICE 审中-公开
标题翻译：基于纳米级的机械切换装置
公开(公告)号：WO2014142910A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/031607
申请日：2013-03-14
申请人： INTEL CORPORATION , PAWASHE, Chytra , KIM, Raseong , KIM, Seiyon , KUHN, Kelin J. , MANIPATRUNI, Sasikanth , RIOS, Rafael , YOUNG, Ian A. , LIN, Kevin , CHAUDHRY, Anurag
发明人： PAWASHE, Chytra , KIM, Raseong , KIM, Seiyon , KUHN, Kelin J. , MANIPATRUNI, Sasikanth , RIOS, Rafael , YOUNG, Ian A. , LIN, Kevin , CHAUDHRY, Anurag
IPC分类号： H01L29/00 , B81B7/00
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括设置在设置在基板上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线间隔开。

9. 发明申请

WO2009012053A2 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：隔离三极晶体管在大块基板上制作
公开(公告)号：WO2009012053A2
公开(公告)日：2009-01-22
申请号：PCT/US2008/068855
申请日：2008-06-30
申请人： INTEL CORPORATION , RIOS, Rafael , KAVALIEROS, Jack T. , CEA, Stephen M.
发明人： RIOS, Rafael , KAVALIEROS, Jack T. , CEA, Stephen M.
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900°C and around 1100°C for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时之间的时间。

10. 发明申请

WO2016048306A1 SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION 审中-公开
标题翻译：使用纳米线表面终止形成的尺寸TFET晶体管
公开(公告)号：WO2016048306A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057258
申请日：2014-09-24
申请人： INTEL CORPORATION , AVCI, Uygar E. , RIOS, Rafael , KUHN, Kelin J. , YOUNG, Ian A. , WEBER, Justin R.
发明人： AVCI, Uygar E. , RIOS, Rafael , KUHN, Kelin J. , YOUNG, Ian A. , WEBER, Justin R.
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/2003 , H01L29/24 , H01L29/66795 , H01L29/7391
摘要： Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.
摘要翻译：描述了一种TFET，其包括：具有用于形成源极和漏极区域的掺杂区域的纳米线和用于耦合到栅极区域的未掺杂区域; 以及形成在所述纳米线上的第一端接材料; 以及形成在纳米线的与栅极和源极区域重叠的部分上的第二端接材料。描述了另一个TFET，其包括：具有用于形成源极和漏极区域的掺杂区域的纳米线的第一部分和用于耦合到栅极区域的未掺杂区域; 所述纳米线的第二部分垂直于所述第一部分延伸，所述第二部分形成在所述栅极和源极区域旁边; 以及形成在纳米线的第一和第二部分上的端接材料。

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