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11. 发明申请

WO2016010993A1 PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL 审中-公开
标题翻译：具有多级通信信号的编程记忆
公开(公告)号：WO2016010993A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/040327
申请日：2015-07-14
申请人： MICRON TECHNOLOGY, INC.
发明人： RAGHUNATHAN, Shyam Sunder , KALAVADE, Pranav , PARAT, Krishna K. , SRINIVASAN, Charan
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
摘要翻译：提供了用于编程具有多级通过信号的存储器的存储器和方法。一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程被选择被编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。升压可能包括使用多步通过信号。

12. 发明申请

WO2015175170A1 SYSTEM AND METHOD FOR REDUCING DISTURBANCES DURING PROGRAMMING OF SPLIT GATE FLASH MEMORY CELLS 审中-公开
标题翻译：在分离栅闪存存储器单元编程期间减少干扰的系统和方法
公开(公告)号：WO2015175170A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/026809
申请日：2015-04-21
申请人： SILICON STORAGE TECHNOLOGY, INC.
发明人： KIM, Jinho , LY, Anh , MARKOV, Viktor
IPC分类号： G11C16/04 , G11C16/34 , G11C7/02 , G11C16/08 , G11C8/10
CPC分类号： G11C16/14 , G11C7/02 , G11C8/10 , G11C16/0408 , G11C16/0425 , G11C16/08 , G11C16/3427
摘要： An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.
摘要翻译：公开了一种改进的控制门解码设计，用于在闪速存储器单元的编程期间减少干扰。在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。

13. 发明申请

WO2015022741A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2015022741A1
公开(公告)日：2015-02-19
申请号：PCT/JP2013/071954
申请日：2013-08-15
申请人：ルネサスエレクトロニクス株式会社
发明人：澤田　誠二
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G06F21/6218 , G06F3/0623 , G06F3/0638 , G06F3/0683 , G06F12/1408 , G06F21/85 , G11C7/1012 , G11C7/1087 , G11C16/04 , G11C16/0475 , G11C16/06 , G11C16/3427
摘要：　スクランブル部（５０１）は、第１の記憶部（５０２）内のツインセル（５０５）に書込むデータをスクランブルデータを用いてスクランブル処理する。書込み部（５０９）は、第１の記憶部（５０２）内のツインセル（５０５）にスクランブル処理後の書込みデータを書込む。書込み部（５１１）は、第２の記憶部（５０３）内のメモリセル（５１０）にスクランブルデータを書込む。ディスクランブル部（５０４）は、第２の記憶部（５０３）から読出されたスクラブルデータを用いて、第１の記憶部（５０２）から読出されたデータをディスクランブル処理する。
摘要翻译：加扰单元（501）执行使用加扰数据对要写入第一存储单元（502）内的双胞坞（505）的数据进行加扰的处理。写入单元（509）将加扰后的写入数据写入第一存储单元（502）内的双胞坞（505）。写单元（511）将加扰数据写入第二存储单元（503）内的存储单元（510）。使用从第二存储单元（503）读取的加扰数据的解扰单元（504）对从第一存储单元（502）读出的数据执行解扰处理。

14. 发明申请

WO2014163725A1 REDUCING PROGRAM DISTURBS IN NON-VOLATILE MEMORY CELLS 审中-公开
标题翻译：减少非易失性记忆细胞中的程序障碍
公开(公告)号：WO2014163725A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/011606
申请日：2014-01-15
申请人： CYPRESS SEMICONDUCTOR CORPORATION
发明人： HIROSE, Ryan , KOUZNETSOV, Igor , PRABHAKAR, Venkatraman , SHAKERI, Kaveh , GEORGESCU, Bogdan
IPC分类号： G11C16/08 , G11C16/04 , G11C7/00
CPC分类号： G11C16/3427 , G11C11/34 , G11C16/0408 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/30
摘要： A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a nonvolatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.
摘要翻译：提供了非易失性存储器及其操作方法以减少干扰。在一个实施例中，该方法包括将第一正高电压耦合到存储器单元阵列的第一行中的第一全局字线，以及将第二负高电压（VNEG）耦合到阵列的第一列中的第一位线以将偏置施加到所选择的存储器单元中的非易失性存储晶体管，以对所选择的存储单元进行编程。具有小于VNEG的幅度的裕度电压被耦合到阵列的第二行中的第二全局字线，并且耦合到阵列的第二列中的第二位线的抑制电压以减小施加到非易失性存储器晶体管的偏置在未选择的存储器单元中，以减少由于编程而在未选择的存储单元中编程的数据的编程干扰。

15. 发明申请

WO2014137928A2 DYNAMIC ERASE DEPTH FOR IMPROVED ENDURANCE OF NON-VOLATILE MEMORY 审中-公开
标题翻译：用于改善非易失性存储器耐久性的动态擦除深度
公开(公告)号：WO2014137928A2
公开(公告)日：2014-09-12
申请号：PCT/US2014019995
申请日：2014-03-03
申请人： SANDISK TECHNOLOGIES INC
发明人： DUTTA DEEPANSHU , LAI CHUN-HUNG , LEE SHIH-CHUNG , OOWADA KEN , HIGASHITANI MASAAKI
IPC分类号： G11C16/34
CPC分类号： G11C16/14 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/3427 , G11C16/3445 , G11C16/349
摘要： Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.
摘要翻译：公开了通过动态擦除深度改进非易失性存储器的耐久性。一组存储器单元被擦除。然后，至少一些擦除的存储单元被编程。对存储器单元进行编程通常会影响想要保持擦除的那些存储器单元的擦除阈值分布。可以根据编程操作如何影响擦除阈值分布来调整下一次擦除的擦除深度。作为一个例子，擦除分布的上部尾部在编程之后被测量。在一个实施例中，上尾越高，下次擦除越浅。这有助于提高耐力。在一个实施例中，通过确定合适的擦除验证电平来调整擦除深度。除了调整擦除验证电平（或除此之外），擦除验证通过之后执行的擦除脉冲的数量可被调整以调整擦除深度。

16. 发明申请

WO2014022281A1 BITLINE VOLTAGE REGULATION IN NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的电压调节
公开(公告)号：WO2014022281A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/052504
申请日：2013-07-29
申请人： SPANSION LLC
发明人： BINBOGA, Evrim
IPC分类号： G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/10 , G11C16/24 , G11C16/3427
摘要： Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell, Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted. neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a "source" bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.
摘要翻译：提供了系统和方法以最小化非易失性存储器阵列的非目标存储器单元中的写入干扰状况。提供位线驱动器电路以控制施加到目标存储器单元的位线和非目标存储器单元的相邻位线的斜坡电压。各种实施例有利地通过施加受控电压信号来维持存储在非目标存储器单元中的数据的完整性到相邻小区的先前浮动的位线，以减少非目标的源和漏节点之间的电位差。在目标存储器单元的写操作期间的相邻存储单元。在另一个实施例中，在漏极偏置电压的斜坡期间，增加的源极偏置电压被施加在目标单元的“源”位线上，然后在写入操作期间被减小到接地或接地电位。

17. 发明申请

WO2013191870A1 FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM 审中-公开
标题翻译：具有指定读取SCRUB算法的闪存
公开(公告)号：WO2013191870A1
公开(公告)日：2013-12-27
申请号：PCT/US2013/043692
申请日：2013-05-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： SPROUSE, Steven, T. , BAUCHE, Alexandra , HUANG, Yichao , CHEN, Jian , HUANG, Jianmin , LEE, Dana
IPC分类号： G11C16/34
CPC分类号： G11C16/3418 , G11B20/18 , G11B20/1883 , G11C16/3427 , G11C16/3431
摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.
摘要翻译：已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。块刷新过程可以包括在后台操作期间将数据从块复制到新块中。

18. 发明申请

WO2013028721A1 READ COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF NON-VOLATILE STORAGE 审中-公开
标题翻译：阅读对非易失性存储部分编程块的补偿
公开(公告)号：WO2013028721A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/051797
申请日：2012-08-22
申请人： SANDISK TECHNOLOGIES, INC. , LEE, Dana , OOWADA, Ken
发明人： LEE, Dana , OOWADA, Ken
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3427 , G11C11/5642
摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.
摘要翻译：提供了部分编程的非易失性存储块的读取补偿。在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。如果是这样，那么在阅读请求的页面时可以做出适当的补偿。该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。赔偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。该补偿可以补偿所请求页面的阈值电压分布的变化，该偏移将从其他页面的后续编程发生。

19. 发明申请

WO2012151454A3 THERMAL TREATMENT OF FLASH MEMORIES 审中-公开
标题翻译：闪存记忆体的热处理
公开(公告)号：WO2012151454A3
公开(公告)日：2013-01-24
申请号：PCT/US2012036420
申请日：2012-05-04
申请人： MICRON TECHNOLOGY INC , VANALLI GIAN PIETRO , CORNO STEFANO , CAMPARDO GIOVANNI , VISCONTI ANGELO , BELTRAMI SILVIA , PETRUSHIN ALEXEY
发明人： VANALLI GIAN PIETRO , CORNO STEFANO , CAMPARDO GIOVANNI , VISCONTI ANGELO , BELTRAMI SILVIA , PETRUSHIN ALEXEY
IPC分类号： G11C16/02
CPC分类号： G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
摘要翻译：存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。如果需要，加热后，可以刷新存储器。在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

20. 发明申请

WO2013006354A2 PROGRAMMING METHODS AND MEMORIES 审中-公开
标题翻译：编程方法和记忆
公开(公告)号：WO2013006354A2
公开(公告)日：2013-01-10
申请号：PCT/US2012/044519
申请日：2012-06-28
申请人： MICRON TECHNOLOGY, INC. , SARIN, Vishal , RADKE, William H. , ROOHPARVAR, Frankie F.
发明人： SARIN, Vishal , RADKE, William H. , ROOHPARVAR, Frankie F.
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454
摘要： Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
摘要翻译：公开了对存储器和存储器进行编程的方法。在至少一个实施例中，通过确定所选择的单元的预定阈值电压来对存储器进行编程，其中使用所选单元的至少一个相邻单元的预定阈值电压值来确定预定阈值电压。

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