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91. 发明申请

WO2013078294A2 LAYOUTS FOR MEMORY AND LOGIC CIRCUITS IN A SYSTEM-ON-CHIP 审中-公开
标题翻译：用于系统即插即用中的存储器和逻辑电路的布线
公开(公告)号：WO2013078294A2
公开(公告)日：2013-05-30
申请号：PCT/US2012/066236
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD. , HOLT, Joseph , MADER, Roy , GREINER, Brandon , ANDERSON, Scott B.
发明人： HOLT, Joseph , MADER, Roy , GREINER, Brandon , ANDERSON, Scott B.
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G11C5/06 , G06F17/505 , G06F17/5072 , G11C5/02 , H01L27/0207 , H01L27/105
摘要： An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits.
摘要翻译：一种集成电路，包括多个存储电路和多个逻辑电路。多个存储电路沿着多行和多列布置在管芯上。每个存储器电路包括多个存储单元。多个逻辑电路沿着多个行和多个列被布置在多个存储器电路之间的管芯上。多个逻辑电路被配置为与一个或多个存储器电路进行通信。

92. 发明申请

WO2013072773A3 DATA PATH ACCELERATION USING HW VIRTUALIZATION 审中-公开
公开(公告)号：WO2013072773A3
公开(公告)日：2013-05-23
申请号：PCT/IB2012/002889
申请日：2012-11-16
申请人： MARVELL WORLD TRADE LTD. , KARDASHOV, Timor , KOVALENKO, Maxim
发明人： KARDASHOV, Timor , KOVALENKO, Maxim
IPC分类号： H04L12/753
摘要： A processing core includes a packet classifier, implemented in a single processing core, configured to classify incoming data packets into first data packets of a known data packet flow and into second data packets of an unknown data packet flow, a first path thread, implemented in the single processing core, configured to process ones of the first data packets at least by forwarding the first data packets to a destination that corresponds to a previously determined destination associated with the known data packet flow, and a second path thread, implemented in the single processing core, configured to process a received second data packet at least to determine a new data packet flow for the second data packet.

93. 发明申请

WO2013068844A2 NETWORK ACCESS MECHANISM BASED ON POWER 审中-公开
标题翻译：基于功率的网络访问机制
公开(公告)号：WO2013068844A2
公开(公告)日：2013-05-16
申请号：PCT/IB2012/002814
申请日：2012-11-05
申请人： MARVELL WORLD TRADE LTD.
发明人： RAOUL, Yann
IPC分类号： H04L12/413
CPC分类号： H04W48/14 , H04W48/02 , H04W74/08
摘要： Systems and methods for accessing a contention-based communications network are provided. In systems and methods for accessing a contention-based communications network, an access point in the network is created. The access point is a first node connected to the network configured to receive a request from a second node to gain access to the network. A power of a signal transmitted between the access point and the second node is measured. A probability that the second node will access the network is determined based on the measured power of the signal transmitted between the access point and the second node. A determination of whether to permit the second node to gain access to the network is made based on the determined probability.
摘要翻译：提供了用于访问基于竞争的通信网络的系统和方法。在用于访问基于争用的通信网络的系统和方法中，创建网络中的接入点。接入点是连接到网络的第一节点，被配置为从第二节点接收请求以获得对网络的访问。测量在接入点和第二节点之间传输的信号的功率。基于在接入点和第二节点之间传输的信号的测量功率来确定第二节点将访问网络的概率。基于确定的概率来确定是否允许第二节点访问网络。

94. 发明申请

WO2013067137A2 SCALABLE SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：可扩展连续逼近 - 寄存器模拟到数字转换器
公开(公告)号：WO2013067137A2
公开(公告)日：2013-05-10
申请号：PCT/US2012/062990
申请日：2012-11-01
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Sehat , CESURA, Giovanni, Antonio , REZZI, Francesco , CASTELLO, Rinaldo
发明人： SUTARDJA, Sehat , CESURA, Giovanni, Antonio , REZZI, Francesco , CASTELLO, Rinaldo
IPC分类号： H03M1/00
CPC分类号： H03M1/20 , A01K79/00 , A23K50/80 , H03M1/002 , H03M1/0643 , H03M1/0678 , H03M1/1076 , H03M1/121 , H03M1/468
摘要： A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.
摘要翻译：一种包括被配置为产生时钟的时钟发生器的系统; 多个模数转换器，每个被配置为基于时钟转换信号，并且响应于基于时钟转换信号来输出第一位数; 以及平均模块，被配置为从所述多个模数转换器中的每一个接收所述第一数量的位，并输出第二数量的位。第二位数大于第一位数。

95. 发明申请

WO2013066752A1 DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：差分放大器
公开(公告)号：WO2013066752A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062144
申请日：2012-10-26
申请人： MARVELL WORLD TRADE, LTD. , CYRUSIAN, Sasan , UEHARA, Gregory T.
发明人： CYRUSIAN, Sasan , UEHARA, Gregory T.
IPC分类号： H03F3/45
CPC分类号： H03F3/45237 , H03F3/45 , H03F3/4565
摘要： Aspects of the disclosure provide a differential amplifier. The differential amplifier includes a first pair of complementary transistors, a second pair of complementary transistors, and a current source. First control terminals of the first pair of complementary transistors are coupled to a first input node of the differential amplifier and first driving terminals of the first pair of complementary transistors are coupled to a first output node of the differential amplifier for driving a load. Second control terminals of the second pair of complementary transistors are coupled to a second input node of the differential amplifier and second driving terminals of the second pair of complementary transistors coupled to a second output node of the differential amplifier for driving the load. The current source is configured to maintain a substantially constant total current flow through the first pair of complementary transistors and the second pair of complementary transistors.
摘要翻译：本公开的方面提供了差分放大器。差分放大器包括第一对互补晶体管，第二对互补晶体管和电流源。第一对互补晶体管的第一控制端子耦合到差分放大器的第一输入节点，第一对互补晶体管的第一驱动端耦合到差分放大器的第一输出节点，用于驱动负载。第二对互补晶体管的第二控制端子耦合到差分放大器的第二输入节点，并且耦合到差分放大器的第二输出节点的第二对互补晶体管的第二驱动端子用于驱动负载。电流源被配置为保持通过第一对互补晶体管和第二对互补晶体管的基本恒定的总电流。

96. 发明申请

WO2013066739A1 METHOD AND APPARATUS FOR AUTOMATICALLY DETECTING A PHYSICAL LAYER (PHY) MODE OF A DATA UNIT IN A WIRELESS LOCAL AREA NETWORK (WLAN) 审中-公开
标题翻译：用于在无线局域网（WLAN）中自动检测数据单元的物理层（PHY）模式的方法和装置
公开(公告)号：WO2013066739A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062039
申请日：2012-10-26
申请人： MARVELL WORLD TRADE LTD. , ZHANG, Hongyuan
发明人： ZHANG, Hongyuan
IPC分类号： H04L1/00 , H04L27/26 , H04L5/00
CPC分类号： H04L27/2613 , H04L1/00 , H04L5/0007 , H04L5/0023 , H04L5/0048 , H04L5/0064 , H04L27/2602
摘要： In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, the data unit is generated to include a first long training field when the data unit is to be transmitted in a normal mode. The data unit is generated to include a second long training field when the data unit is to be transmitted in a low bandwidth mode. The first training field and the second training field are configured such that a receiving device can auto-detect whether the data unit corresponds to the low bandwidth mode or the normal mode.
摘要翻译：在用于生成经由通信信道传输的物理层（PHY）数据单元的方法中，生成数据单元以在正常模式下发送数据单元时包括第一长训练场。当数据单元要以低带宽模式发送时，生成数据单元以包括第二长训练场。第一训练场和第二训练场被配置为使得接收设备可以自动检测数据单元是否对应于低带宽模式或正常模式。

97. 发明申请

WO2013063574A1 DATA UNIT FORMAT SIGNALLING FOR WIRELESS LOCAL AREA NETWORKS (WLANS) 审中-公开
标题翻译：无线局域网（WLANS）的数据单元格式信令
公开(公告)号：WO2013063574A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/062427
申请日：2012-10-29
申请人： MARVELL WORLD TRADE LTD. , ZHANG, Hongyuan , BANERJEA, Raja
发明人： ZHANG, Hongyuan , BANERJEA, Raja
IPC分类号： H04L27/26 , H04L1/00
CPC分类号： H04L27/2649 , H04L1/0003 , H04L1/0009 , H04L1/08 , H04L27/2613 , H04L27/2666 , H04W84/12
摘要： One or more symbols of the SIG field ar modulated using a first symbol constellation rotation (e.g. zero degrees) to indicate to a receiver that a data unit is a single-user data unit or with a second rotation (e.g. 90 degrees) to indicate to a receiver that the data unit is a multi-user data unit.
摘要翻译：使用第一符号星座旋转（例如零度）对SIG场的一个或多个符号进行调制，以向接收机指示数据单元是单用户数据单元或具有第二旋转（例如90度）以指示数据单元是多用户数据单元的接收器。

98. 发明申请

WO2013028435A1 PACKAGE-ON-PACKAGE STRUCTURES 审中-公开
标题翻译：包装封装结构
公开(公告)号：WO2013028435A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/050953
申请日：2012-08-15
申请人： Marvell World Trade Ltd. , KAO, Huahung , LIOU, Shiann-Ming
发明人： KAO, Huahung , LIOU, Shiann-Ming
IPC分类号： H01L25/10
CPC分类号： H01L25/50 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11849 , H01L2224/13022 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81801 , H01L2224/838 , H01L2224/92247 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.
摘要翻译：本公开的实施例提供了一种包装装置，包括底部包装和第二包装。第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。此外，顶侧限定基本平坦的表面。第一封装还包括耦合到衬底层的底侧的管芯。第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

99. 发明申请

WO2013028406A1 METHOD AND APPARATUS FOR LED LIGHTING 审中-公开
标题翻译： LED照明的方法和装置
公开(公告)号：WO2013028406A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/050739
申请日：2012-08-14
申请人： MARVELL WORLD TRADE, LTD. , ZHANG, Wanfeng , OH, InHwan
发明人： ZHANG, Wanfeng , OH, InHwan
IPC分类号： H05B33/08
CPC分类号： H05B33/0815
摘要： Aspects of the disclosure provide a circuit. The circuit includes a first switch, a second switch and a controller. The first switch is switched on and off to allow a boost circuit to transfer electric energy from an input power supply to a capacitor to generate an intermediate power supply having a higher voltage than the input power supply. The second switch is switched on and off to allow a buck circuit to provide a driving voltage based on the intermediate power supply to drive a load device, and to regulate a current to the load device. The controller is configured to provide a first signal to the first switch and a second signal to the second switch to switch on and off the first switch and the second switch.
摘要翻译：本公开的方面提供电路。电路包括第一开关，第二开关和控制器。第一开关被接通和关断以允许升压电路将电能从输入电源传送到电容器以产生具有比输入电源更高的电压的中间电源。第二开关被接通和关断以允许降压电路基于中间电源提供驱动电压以驱动负载装置，并调节到负载装置的电流。控制器被配置为向第一开关提供第一信号，并将第二信号提供给第二开关以接通和断开第一开关和第二开关。

100. 发明申请

WO2013027121A1 PROTECTION CIRCUIT IN TRIAC APPLICATIONS 审中-公开
标题翻译： TRIAC应用中的保护电路
公开(公告)号：WO2013027121A1
公开(公告)日：2013-02-28
申请号：PCT/IB2012/001880
申请日：2012-07-25
申请人： MARVELL WORLD TRADE, LTD. , CHUI, Siew, Yong
发明人： CHUI, Siew, Yong
IPC分类号： H02H9/00 , G05F1/56
CPC分类号： H05B39/02 , H02H7/222 , H03K17/0822 , H03K2017/6875
摘要： A circuit is disclosed that includes a transistor configured to control energy entering into the circuit from a power supply. A capacitor is coupled to the transistor to store the energy that enters the circuit, and a protection circuit is provided to prevent undesired conduction of the transistor due to coupling of step voltage changes in the power supply voltage to the gate electrode of the transistor.
摘要翻译：公开了一种电路，其包括被配置为控制从电源进入电路的能量的晶体管。电容器耦合到晶体管以存储进入电路的能量，并且提供保护电路以防止由于电源电压中的阶跃电压变化与晶体管的栅电极的耦合而引起的晶体管的不期望的导通。

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