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1. 发明申请

WO2014144146A1 HIGH SPEED LATCH WITH OVER VOLTAGE PROTECTION AND INTEGRATED SUMMING NODES 审中-公开
标题翻译：具有过电压保护和集成节能的高速锁具
公开(公告)号：WO2014144146A1
公开(公告)日：2014-09-18
申请号：PCT/US2014/028434
申请日：2014-03-14
申请人： MARVELL WORLD TRADE LTD. , CYRUSIAN, Sasan
发明人： CYRUSIAN, Sasan
IPC分类号： H03K5/24 , H03F3/00
CPC分类号： H03K3/0375 , H02H3/20 , H02H7/1252 , H02H9/04 , H02H9/046 , H02K5/24 , H03K5/24
摘要： A latch (300) includes a current source (320), an input amplifier (316), and a latch output circuit (336). The current source is configured to output a current based on a voltage source (332). The input amplifier is configured to receive a differential analog input signal (308) including a first differential input (308-1) and a second differential input (308-2) and selectively provide the current based on the first differential input and the second differential input. A latch output circuit (336) is configured to selectively output a differential digital (312) output signal including a first differential output (312-1) and a second differential output (312-2). The latch output circuit includes an over voltage protection circuit (304) configured to receive the current output from the input amplifier (316), receive the voltage source limit (396), and output a modified differential digital output signal (312) based on a comparison between a voltage corresponding to each of the first differential output (312-1) and the second differential output (312-2) and the voltage source limit (396).
摘要翻译：锁存器（300）包括电流源（320），输入放大器（316）和锁存器输出电路（336）。电流源被配置为基于电压源输出电流（332）。输入放大器被配置为接收包括第一差分输入（308-1）和第二差分输入（308-2）的差分模拟输入信号（308），并且基于第一差分输入和第二差分输入输入。闩锁输出电路（336）被配置为选择性地输出包括第一差分输出（312-1）和第二差分输出（312-2）的差分数字（312）输出信号。闩锁输出电路包括被配置为接收来自输入放大器（316）的电流输出的过电压保护电路（304），接收电压源极限（396），并且输出修改后的差分数字输出信号（312），基于与第一差分输出（312-1）和第二差分输出（312-2）中的每一个相对应的电压和电压源极限（396）之间的比较。

2. 发明申请

WO2013066754A1 REGULATED POWER SUPPLY VOLTAGE FOR DIGITAL CIRCUITS 审中-公开
标题翻译：数字电路的调节电源电压
公开(公告)号：WO2013066754A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062151
申请日：2012-10-26
申请人： MARVELL WORLD TRADE, LTD. , CYRUSIAN, Sasan
发明人： CYRUSIAN, Sasan
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3296 , Y02D10/172
摘要： An integrated circuit (IC) includes a sensing circuit that outputs a sense signal. An external power supply may receive the sense signal and adjust a power supply voltage to the IC. The sensing circuit may comprise an oscillatory circuit that outputs a time-varying signal. The sense signal is based on the time-varying signal.
摘要翻译：集成电路（IC）包括输出感测信号的感测电路。外部电源可以接收感测信号并调节IC的电源电压。感测电路可以包括输出时变信号的振荡电路。感测信号基于时变信号。

3. 发明申请

WO2012078733A1 DIGITAL TO ANALOG CONVERTER CIRCUITS AND METHODS 审中-公开
标题翻译：数字到模拟转换器电路和方法
公开(公告)号：WO2012078733A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/063706
申请日：2011-12-07
申请人： MARVELL WORLD TRADE LTD , CYRUSIAN, Sasan
发明人： CYRUSIAN, Sasan
IPC分类号： H03M1/00
CPC分类号： H03M1/0845 , H03M1/00 , H03M1/0682 , H03M1/12 , H03M1/742 , H03M1/747 , H04B3/54 , H04L25/067 , H04L27/2647
摘要： The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit.
摘要翻译：本公开提供了改进的DAC电路和方法。在一个实施例中，数模转换器接收数字信号并输出对应于数字信号的第一模拟输出信号。当前缓冲器接收第一模拟输出信号并产生模拟输出电流。电流输出数模转换器和电流缓冲器构成在集成电路上，模拟输出电流耦合到集成电路的引脚。集成电路的引脚接收模拟输出电流，并将模拟输出电流提供给集成电路外部的附加电路。

4. 发明申请

WO2013066752A1 DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：差分放大器
公开(公告)号：WO2013066752A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062144
申请日：2012-10-26
申请人： MARVELL WORLD TRADE, LTD. , CYRUSIAN, Sasan , UEHARA, Gregory T.
发明人： CYRUSIAN, Sasan , UEHARA, Gregory T.
IPC分类号： H03F3/45
CPC分类号： H03F3/45237 , H03F3/45 , H03F3/4565
摘要： Aspects of the disclosure provide a differential amplifier. The differential amplifier includes a first pair of complementary transistors, a second pair of complementary transistors, and a current source. First control terminals of the first pair of complementary transistors are coupled to a first input node of the differential amplifier and first driving terminals of the first pair of complementary transistors are coupled to a first output node of the differential amplifier for driving a load. Second control terminals of the second pair of complementary transistors are coupled to a second input node of the differential amplifier and second driving terminals of the second pair of complementary transistors coupled to a second output node of the differential amplifier for driving the load. The current source is configured to maintain a substantially constant total current flow through the first pair of complementary transistors and the second pair of complementary transistors.
摘要翻译：本公开的方面提供了差分放大器。差分放大器包括第一对互补晶体管，第二对互补晶体管和电流源。第一对互补晶体管的第一控制端子耦合到差分放大器的第一输入节点，第一对互补晶体管的第一驱动端耦合到差分放大器的第一输出节点，用于驱动负载。第二对互补晶体管的第二控制端子耦合到差分放大器的第二输入节点，并且耦合到差分放大器的第二输出节点的第二对互补晶体管的第二驱动端子用于驱动负载。电流源被配置为保持通过第一对互补晶体管和第二对互补晶体管的基本恒定的总电流。

5. 发明申请

WO2012078738A1 INTEGRATOR INPUT ERROR CORRECTION CIRCUIT AND CIRCUIT METHOD 审中-公开
标题翻译：集成输入错误校正电路和电路方法
公开(公告)号：WO2012078738A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/063712
申请日：2011-12-07
申请人： MARVELL WORLD TRADE LTD , CYRUSIAN, Sasan
发明人： CYRUSIAN, Sasan
IPC分类号： G06G7/18
CPC分类号： H03F3/38 , H03F3/217 , H03F3/26
摘要： A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.
摘要翻译：电路包括第一放大器和第二放大器，其中第一放大器被配置为在第一放大器的第一输入处接收输入电流，并且第一op-mp的输出被配置为驱动第二放大器的第一输入。电路还包括选择性地耦合到第二放大器的第一输入的上拉电流源，以及选择性地耦合到第二放大器的第一输入的下拉电流源。如果输入电流的绝对值大于预定义的阈值电流：i）上拉电流源被配置成驱动电流进入第二放大器的第一输入端用于输入电流的第一极性，以及ii）下拉电流源被配置为从输入电流的第二极性吸收来自第二放大器的第一输入端的电流。

6. 发明申请

WO2012079090A3 FAST POWER UP COMPARATOR 审中-公开
标题翻译：快速上电比较器
公开(公告)号：WO2012079090A3
公开(公告)日：2014-04-10
申请号：PCT/US2011064489
申请日：2011-12-12
申请人： MARVELL WORLD TRADE LTD , CYRUSIAN SASAN
发明人： CYRUSIAN SASAN
IPC分类号： H03K5/22
CPC分类号： G06F1/3287 , G06F1/3234 , H03F1/0266 , H03F1/0272 , H03F1/0283 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F3/3022 , H03F3/3033 , H03F3/45183 , H03F3/4521 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/264 , H03F2200/27 , H03F2200/321 , H03F2200/75 , H03F2200/78 , H03F2203/45466 , H03F2203/45471 , H03F2203/45504 , H03F2203/45506 , H03F2203/45512 , H03F2203/45674 , H03F2203/45726 , H03F2203/7203
摘要： A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.
摘要翻译：一种电路方法包括周期性地增加比较器的差分级的尾电流，以将差分级周期性地上电到上电状态，并且周期性地减小差分级的尾电流以周期性地将差分级降低到低电力状态。尾电流的周期性增加和尾电流的周期性减小是用于将差动级上电到上电状态的异步操作，并且将差动级下电至低功率状态。周期性地增加尾电流并且不同步地周期性地减小尾电流以将差分级上电到上电状态，并将差分级上电到低功率状态，在信号比较期间提供低噪声和高速度。

7. 发明申请

WO2012079090A2 FAST POWER UP COMPARATOR 审中-公开
标题翻译：快速上电比较器
公开(公告)号：WO2012079090A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/064489
申请日：2011-12-12
申请人： MARVELL WORLD TRADE LTD , CYRUSIAN, Sasan
发明人： CYRUSIAN, Sasan
IPC分类号： H03F3/45 , H03G3/20
CPC分类号： G06F1/3287 , G06F1/3234 , H03F1/0266 , H03F1/0272 , H03F1/0283 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F3/3022 , H03F3/3033 , H03F3/45183 , H03F3/4521 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/264 , H03F2200/27 , H03F2200/321 , H03F2200/75 , H03F2200/78 , H03F2203/45466 , H03F2203/45471 , H03F2203/45504 , H03F2203/45506 , H03F2203/45512 , H03F2203/45674 , H03F2203/45726 , H03F2203/7203
摘要： A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.
摘要翻译：一种电路方法包括周期性地增加比较器的差分级的尾电流，以将差分级周期性地上电到上电状态，并且周期性地减小差分级的尾电流以周期性地将差分级降低到低电力状态。尾电流的周期性增加和尾电流的周期性减少是异步操作，用于将差动级上电至上电状态，并将差分级上电至低功率状态。周期性地增加尾电流并且不同步地周期性地减小尾电流以将差动级上电到上电状态，并且将差动级下电到低功率状态，在信号比较期间提供低噪声和高速度。

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