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1. 发明申请

US20100041195A1 METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS 有权
标题翻译：用于高功率器件应用的硅碳化物自对准外延MOSFET的制造方法
公开(公告)号：US20100041195A1
公开(公告)日：2010-02-18
申请号：US12603603
申请日：2009-10-22
申请人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
发明人： Christopher Harris , Kent Bertilsson , Andrei Konstantinov
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/66068 , Y10S438/903 , Y10S438/969
摘要： A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.
摘要翻译：自对准的碳化硅功率金属氧化物半导体场效应晶体管包括形成在第一层中的沟槽，其具有在沟槽内外延再生长的基极区域和源极区域。通过源区域形成窗口，并且在沟槽的中间区域内形成窗口。源极触点形成在与基极和源极区域接触的窗口内。栅极氧化层形成在沟槽的周边区域和第一层的表面上的源极和基极区域上。在沟槽的周边区域的基极区域上方的栅极氧化层上形成栅电极，在第一层的第二面上形成漏电极。

2. 发明申请

US20090236668A1 METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE 有权
标题翻译：改善SiGe双极器件写入漏电的方法
公开(公告)号：US20090236668A1
公开(公告)日：2009-09-24
申请号：US12476994
申请日：2009-06-02
申请人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh
发明人： Alan S. Chen , Mark Dyson , Nace M. Rossi , Ranbir Singh
IPC分类号： H01L27/102
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66272 , H01L29/7378 , Y10S438/969
摘要： The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
摘要翻译：本发明在一个方面提供了一种用于制造半导体器件的方法，其包括通过发射极层中的开口进行蚀刻以从暴露掺杂的皿的下面的氧化物层形成空腔。通过调整工艺参数以在第一SiGe层中引起应变，在空腔内和掺杂槽之上形成其中具有Ge浓度的第一硅/锗（SiGe）层。在第一SiGe层上形成第二SiGe层，并且在第二SiGe层上形成覆盖层。

3. 发明申请

US20050202612A1 Thin film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20050202612A1
公开(公告)日：2005-09-15
申请号：US11123496
申请日：2005-05-04
申请人： Takuo Tamura , Kiyoshi Ogata , Yoichi Takahara , Kazuhiko Horikoshi , Hironaru Yamaguchi , Makoto Ohkura , Hironobu Abe , Masakazu Saitou , Yoshinobu Kimura , Toshihiko Itoga
发明人： Takuo Tamura , Kiyoshi Ogata , Yoichi Takahara , Kazuhiko Horikoshi , Hironaru Yamaguchi , Makoto Ohkura , Hironobu Abe , Masakazu Saitou , Yoshinobu Kimura , Toshihiko Itoga
IPC分类号： H01L21/205 , H01L21/20 , H01L21/336 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66757 , H01L29/78675 , Y10S438/969
摘要： An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.
摘要翻译：激光照射多次非晶硅膜以使由多个晶粒构成的膜同时抑制邻接晶粒的边界处的突起的形成，以实现多晶硅薄膜晶体管，其至少部分地在其中晶粒簇或至少两个晶粒的聚集体，在平面（111）中具有优选的取向，并且具有高电子迁移率为200cm 2 / Vs以上。

4. 发明申请

US20050090081A1 Single electron transistor manufacturing method by electro-migration of metallic nanoclusters 有权
标题翻译：单电子晶体管制造方法通过金属纳米团簇的电迁移
公开(公告)号：US20050090081A1
公开(公告)日：2005-04-28
申请号：US10695479
申请日：2003-10-28
申请人： Danilo Mascolo , Rossana Scaldaferri , Teresa Napolitano , Valeria Casuscelli , Luigi Occhipinti
发明人： Danilo Mascolo , Rossana Scaldaferri , Teresa Napolitano , Valeria Casuscelli , Luigi Occhipinti
IPC分类号： B82B1/00 , B82B3/00 , H01L21/335 , H01L29/76 , H01L49/00 , C30B1/00
CPC分类号： B82B3/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L29/66439 , H01L49/006 , Y10S438/969
摘要： A method manufactures a single electron transistor device by electro-migration of nanocluster wherein said nanoclusters are metallically passivated and forced to assembly over a lithographic patterned substrate under control of a non homogeneous electric field at room temperature. A controlled migration and the desired location of the metallic passivated nanoclusters are based on a dielectrophoretic process.
摘要翻译：一种方法通过电纳米聚集体的电迁移制造单电子晶体管器件，其中所述纳米簇在金属上被钝化并且在室温下在非均匀电场的控制下被迫在光刻图案化衬底上组装。金属钝化纳米团簇的受控迁移和所需位置基于介电电泳过程。

5. 发明授权

US06884699B1 Process and unit for production of polycrystalline silicon film 有权
标题翻译：生产多晶硅膜的工艺和单元
公开(公告)号：US06884699B1
公开(公告)日：2005-04-26
申请号：US10148562
申请日：2000-10-06
申请人： Tetsuya Ogawa , Hidetada Tokioka , Junichi Nishimae , Tatsuki Okamoto , Yukio Sato , Mitsuo Inoue , Mitsutoshi Miyasaka , Hiroaki Jiroku
发明人： Tetsuya Ogawa , Hidetada Tokioka , Junichi Nishimae , Tatsuki Okamoto , Yukio Sato , Mitsuo Inoue , Mitsutoshi Miyasaka , Hiroaki Jiroku
IPC分类号： C23C14/58 , H01L21/20 , H01L21/336 , H01L21/00 , H01L21/331 , H01L21/26
CPC分类号： C23C14/5813 , B23K26/0604 , B23K26/0738 , B23K26/0838 , B23K26/352 , B23K2101/40 , B23K2103/52 , H01L21/02532 , H01L21/02678 , H01L21/02691 , H01L29/66757 , Y10S438/969
摘要： A process for making a polycrystalline silicon film includes forming, on a glass substrate, an amorphous silicon film having a first region and a second region that contacts the first region, forming a first polycrystalline portion by irradiating the first region of the amorphous silicon film with laser light having a wavelength not less than 390 nm and not more than 640 nm and forming a second polycrystalline portion that contacts the first polycrystalline portion by irradiating the second region and the portion of the region of the first polycrystalline portion that contacts the second region of the amorphous silicon film with the laser light.
摘要翻译：一种制造多晶硅膜的方法包括在玻璃基板上形成具有与第一区域接触的第一区域和第二区域的非晶硅膜，通过用非晶硅膜的第一区域照射非晶硅膜形成第一多晶部分，具有不小于390nm且不大于640nm的波长的激光，并且通过照射第二区域和形成与第一多晶部分接触的第二多晶部分的区域的部分形成第二多晶部分，具有激光的非晶硅膜。

6. 发明申请

US20040248352A1 High performance vertical PNP transistor method 失效
标题翻译：高性能垂直PNP晶体管方法
公开(公告)号：US20040248352A1
公开(公告)日：2004-12-09
申请号：US10863630
申请日：2004-06-08
发明人： Peter B. Gray , Jeffrey B. Johnson
IPC分类号： H01L021/8238
CPC分类号： H01L27/0826 , H01L21/82285 , Y10S438/969
摘要： The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.
摘要翻译：本发明包括用于制造用于BiCMOS器件的高性能垂直NPN和PNP晶体管的方法和结果。所产生的高性能垂直PNP晶体管包括包括硅和锗的发射极区域，并且其PNP发射极与NPN晶体管的基极共享单层硅。该方法为CMOS和双极器件的常规制造工艺增加了两个附加的掩模步骤，因此代表了整个工艺流程的微小添加。所得到的结构显着增强了PNP器件的性能。

7. 发明授权

US06407014B1 Method achieving higher inversion layer mobility in novel silicon carbide semiconductor devices 失效
标题翻译：在新型碳化硅半导体器件中实现更高反型层迁移率的方法
公开(公告)号：US06407014B1
公开(公告)日：2002-06-18
申请号：US09464862
申请日：1999-12-16
申请人： Dev Alok
发明人： Dev Alok
IPC分类号： H01L21302
CPC分类号： H01L29/7802 , H01L21/02532 , H01L21/02667 , H01L21/0445 , H01L21/049 , H01L21/2022 , H01L29/1608 , H01L29/66068 , Y10S438/966 , Y10S438/969
摘要： The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required. The method includes the steps of: (a) amorphizing the silicon carbide in at least one region of a monocrystalline silicon carbide substrate by ion implantation; (b) removing at least an effective amount of the carbon resulting from amorphizing the silicon carbide with an etchant effective to selectively remove carbon from the amorphized silicon carbide to produce an amorphous silicon-rich region; and (c) forming an oxide on the etched surface to provide a device which has an oxide region on (1) either an amorphous silicon-rich region which is (i) predominantly or entirely amorphous silicon or (ii) a mixture of predominantly amorphous silicon in combination with minor amounts of amorphous silicon carbide and /or silicon dioxide or (2) a monocrystalline silicon region; wherein (1) or (2) is present on a region of a silicon carbide substrate, or (3) a region of a silicon carbide substrate.
摘要翻译：本发明提供了一种在碳化硅顶部生产高质量热生长氧化物的方法。通过在需要或需要氧化物形成的区域中选择性地除去碳化硅中的碳而获得高质量的氧化物。该方法包括以下步骤：（a）通过离子注入使单晶碳化硅衬底的至少一个区域中的碳化硅非晶化;（b）除去至少有效量的由蚀刻剂使碳化硅非晶化所产生的碳有效地从非晶化碳化硅中选择性地除去碳以产生无定形富硅区域; 和（c）在蚀刻表面上形成氧化物以提供在（1）无定形富硅区域上具有氧化物区域的器件，所述非晶硅富集区域是（i）主要或全部非晶硅，或（ii）主要为非晶态的硅与少量非晶碳化硅和/或二氧化硅组合，或（2）单晶硅区;其中（1）或（2）存在于碳化硅衬底的区域上，或（3）碳化硅衬底。

8. 发明授权

US06184059B2 Process of making diamond-metal ohmic junction semiconductor device 失效
标题翻译：制造金刚石金属欧姆结半导体器件的工艺
公开(公告)号：US06184059B2
公开(公告)日：2001-02-06
申请号：US08578373
申请日：1995-12-26
申请人： Keiji Hirabayashi , Masaaki Matsushima
发明人： Keiji Hirabayashi , Masaaki Matsushima
IPC分类号： C04B37/02 , C30B29/04 , H01L21/28 , H01L29/16 , H01L29/43 , H01L29/45 , H01L21/00
CPC分类号： H01L21/043 , H01L29/1602 , H01L29/45 , Y10S438/969
摘要： A diamond product comprising a semiconductor layer having an outer surface region of graphite in contact with the metal electrode to form an ohmic junction with the metal electrode, wherein the outer surface region of graphite has a thickness of at least about 12 Å.
摘要翻译：一种金刚石产品，包括具有与所述金属电极接触的石墨外表面区域以形成与所述金属电极的欧姆结的半导体层，其中所述石墨的外表面区域具有至少约的厚度。

9. 发明授权

US5913135A Method for forming planar field effect transistors with source and drain on oxide and device constructed therefrom 失效
标题翻译：用于形成具有氧化物源极和漏极的平面场效应晶体管的方法及由其构成的器件
公开(公告)号：US5913135A
公开(公告)日：1999-06-15
申请号：US989985
申请日：1997-12-12
申请人： Ih-Chin Chen
发明人： Ih-Chin Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762 , H01L29/06 , H01L29/417 , H01L21/20
CPC分类号： H01L29/66651 , H01L21/76202 , H01L29/0653 , H01L29/41766 , H01L29/41775 , Y10S438/969
摘要： A method for forming a transistor (50) includes forming a first insulating region (16) in the outer surface of a semiconductor body (10) and forming a second insulating region (16) in the outer surface of the semiconductor body (10) and spaced apart from the first insulating region by a region of semiconductor material. The method further includes planarizing the first and second insulating regions and the region of semiconductor material to define a planar surface (17) and forming a conductive source region (34) overlying the first insulating region. The method further includes forming a conductive drain region (36) overlying the second insulating region and forming a conductive gate body (24) overlying the planar surface (17) and spaced apart from the conductive source region (34) and the conductive drain region (36).A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed in the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).
摘要翻译：一种形成晶体管（50）的方法包括在半导体本体（10）的外表面中形成第一绝缘区域（16），并在半导体本体（10）的外表面形成第二绝缘区域（16），以及通过半导体材料的区域与第一绝缘区间隔开。该方法还包括平面化第一和第二绝缘区域和半导体材料的区域以限定平坦表面（17）并且形成覆盖在第一绝缘区域上的导电源区域（34）。该方法还包括形成覆盖第二绝缘区域的导电漏极区域（36），并且形成覆盖平面表面（17）并与导电源区域（34）和导电漏极区域（34）隔开的导电栅极体（24） 36）。提供具有基板（10）的场效应晶体管器件（50）。晶体管（50）包括导电栅极主体（24）和栅极绝缘体层（32），栅极绝缘体层（32）具有与导电栅极主体相邻的平面外表面和平坦的内表面（39）。晶体管还包括形成在衬底中的第一和第二绝缘区域（16）。晶体管（50）还包括形成在第二绝缘区域上的导电漏极区域（36）和形成在第一绝缘区域上并与导电栅极体（24）间隔开的导电源区域（34）（36）。导电漏极区域和导电源区域限定平面内表面（39）的一部分。

10. 发明授权

US5831334A Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon 失效
标题翻译：场效应晶体管包括具有单晶硅和多晶硅的导电插塞
公开(公告)号：US5831334A
公开(公告)日：1998-11-03
申请号：US912899
申请日：1997-08-15
申请人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
发明人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
IPC分类号： H01L21/225 , H01L21/336 , H01L29/08 , H01L29/43
CPC分类号： H01L29/66628 , H01L21/2257 , H01L29/0847 , Y10S438/969
摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.
摘要翻译：一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，以及ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。还要求一种场效应晶体管。

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