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1. 发明授权

US08186051B2 Method for fabricating package substrate and die spacer layers having a ceramic backbone 有权
标题翻译：制造具有陶瓷骨架的封装衬底和管芯间隔层的方法
公开(公告)号：US08186051B2
公开(公告)日：2012-05-29
申请号：US12079785
申请日：2008-03-28
申请人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan , Shankar Ganapathysubramanian
发明人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan , Shankar Ganapathysubramanian
IPC分类号： H05K3/02
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.
摘要翻译：描述了用于制造用于封装衬底和管芯间隔件的层或层的方法。在一个实施方案中，制造层或层以包括位于平面内的多个陶瓷阱并且由金属通孔隔开，陶瓷井中的凹陷被介电填料材料占据。

2. 发明授权

US07656035B2 C4 joint reliability 有权
标题翻译： C4联合可靠性
公开(公告)号：US07656035B2
公开(公告)日：2010-02-02
申请号：US12351689
申请日：2009-01-09
申请人： Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
发明人： Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
IPC分类号： H01L23/485
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05655 , H01L2224/13 , H01L2224/13017 , H01L2224/13099 , H01L2224/16058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00 , H01L2224/05099
摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
摘要翻译：在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底位于模具凸块下方的冶金（UBM）层。有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

3. 发明授权

US07527722B2 Electrochemical mechanical planarization 失效
标题翻译：电化学机械平面化
公开(公告)号：US07527722B2
公开(公告)日：2009-05-05
申请号：US10666476
申请日：2003-09-19
申请人： Sujit Sharan
发明人： Sujit Sharan
IPC分类号： B23H5/06 , B23H3/04
CPC分类号： H01L21/3212 , B24B37/046 , H01L21/32134
摘要： The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad; an anode connected electrically to the wafer carrier; and a power supply connected to the anode and the cathode. The present invention further discloses a method to remove a surface layer from a wafer using a polishing pad, a slurry, and an electrical current.
摘要翻译：本发明公开了一种具有压板的装置，设置在所述压板上的抛光垫; 设置在抛光垫上的浆料分配器; 与抛光垫电连接的阴极; 设置在抛光垫上的晶片载体; 与晶片载体电连接的阳极; 以及连接到阳极和阴极的电源。本发明还公开了一种使用抛光垫，浆料和电流从晶片去除表面层的方法。

4. 发明申请

US20080237844A1 Microelectronic package and method of manufacturing same 审中-公开
标题翻译：微电子封装及其制造方法相同
公开(公告)号：US20080237844A1
公开(公告)日：2008-10-02
申请号：US11729200
申请日：2007-03-28
申请人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan
发明人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan
IPC分类号： H01L23/36
CPC分类号： H01L23/3731 , H01L23/3732 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A microelectronic package includes a package substrate (110, 310, 410), a plurality of dies (120, 610, 630) arranged in a stack (150, 350, 450) above the package substrate, with a first die (121) located above the package substrate at a bottom (151) of the stack and an uppermost die (122) located at a top (152) of the stack, and a plurality of heat spreaders (130, 330, 430, 620) stacked above the first die, with a first heat spreader (131) located above the uppermost die. One of the plurality of heat spreaders is located between each pair of adjacent dies. Each one of the plurality of heat spreaders has an extending portion (132) that extends laterally beyond an edge (123) of an adjacent die, and at least one of the plurality of heat spreaders both provides electrical interconnectivity and thermal conductivity.
摘要翻译：微电子封装包括封装衬底（110,310,410），布置在封装衬底上方的堆叠（150,350,450）中的多个管芯（120,610,630），第一管芯（121）位于在所述堆叠的底部（151）处的所述封装衬底上方，以及位于所述堆叠的顶部（152）处的最上面的模具（122）以及堆叠在所述堆叠的顶部（152）上方的多个散热器（130,330,430,620）模具，第一个散热器（131）位于最上面的模具上方。多个散热器中的一个位于每对相邻的模具之间。多个散热器中的每一个具有横向延伸超过相邻模具的边缘（123）的延伸部分（132），并且多个散热器中的至少一个均提供电互连性和导热性。

5. 发明授权

US07229666B2 Chemical vapor deposition method 失效
标题翻译：化学气相沉积法
公开(公告)号：US07229666B2
公开(公告)日：2007-06-12
申请号：US10912878
申请日：2004-08-06
申请人： Allen P. Mardian , Philip H. Campbell , Craig M. Carpenter , Randy W. Mercil , Sujit Sharan
发明人： Allen P. Mardian , Philip H. Campbell , Craig M. Carpenter , Randy W. Mercil , Sujit Sharan
IPC分类号： C23C16/00
CPC分类号： C23C16/45565 , C23C16/4401 , C23C16/45519
摘要： Methods of chemical vapor deposition include providing a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. At least one process chemical inlet to the deposition chamber is included. A substrate is positioned within the chamber and a process gas is provided over the substrate effective to deposit material onto the substrate. While providing the process gas, a purge gas is emitted into the chamber from a plurality of purge gas inlets comprised by at least one chamber wall surface. The purge gas inlets are separate from the at least one process chemical inlet and the emitting forms an inert gas curtain over the chamber wall surface.
摘要翻译：化学气相沉积的方法包括提供至少部分地由室侧壁和室底壁中的至少一个限定的沉积室。包括沉积室的至少一个工艺化学品入口。衬底定位在腔室内，并且在衬底上方设置有效地将材料沉积到衬底上的工艺气体。在提供工艺气体的同时，净化气体从由至少一个室壁表面包括的多个吹扫气体入口排出到室中。吹扫气体入口与至少一个过程化学品入口分离，并且所述排放物在室壁表面上形成惰性气体窗帘。

6. 发明申请

US20060218762A1 SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER 审中-公开
公开(公告)号：US20060218762A1
公开(公告)日：2006-10-05
申请号：US11421701
申请日：2006-06-01
申请人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
发明人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
IPC分类号： H01L21/00 , H01L21/306 , C23C16/00
CPC分类号： G01F1/40 , G01F1/42 , G01P13/0006 , G01P13/0013 , G01P13/0033 , G05D7/0635 , Y10T137/0396 , Y10T137/7722 , Y10T137/775 , Y10T137/8242
摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.

7. 发明申请

US20060205175A1 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 有权
标题翻译：形成二氧化硅层的方法以及形成沟槽隔离区的方法
公开(公告)号：US20060205175A1
公开(公告)日：2006-09-14
申请号：US11362455
申请日：2006-02-23
申请人： Sujit Sharan , Gurtej Sandhu
发明人： Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.
摘要翻译：形成二氧化硅层的方法包括在基底附近形成高密度等离子体，所述等离子体包含二氧化硅前体; 从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 并且在沉积时以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。另一种方法包括在基底附近形成高密度等离子体; 流入气体进入等离子体，形成二氧化硅的至少一些气体; 将由气体形成的二氧化硅沉积在衬底上; 并且同时沉积二氧化硅，将基底的温度保持在大于或等于约500℃。作为替代方案，该方法可以包括在沉积二氧化硅的同时不用冷却剂气体冷却基底。

8. 发明授权

US07018908B2 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 失效
标题翻译：形成二氧化硅层的方法以及形成沟槽隔离区的方法
公开(公告)号：US07018908B2
公开(公告)日：2006-03-28
申请号：US10815065
申请日：2004-03-30
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L21/76
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： In one aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. In yet another aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) not cooling the substrate with a coolant gas while depositing the silicon dioxide.
摘要翻译：一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体，所述等离子体包含二氧化硅前体; b）从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 和c）在沉积时，以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。另一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）同时沉积二氧化硅，将基底的温度保持在大于或等于约500℃。在另一方面，本发明包括形成二氧化硅层的方法，包括：a）形成高的靠近基底的密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）在沉积二氧化硅的同时不用冷却剂气体冷却衬底。

9. 发明申请

US20050221586A1 Methods and apparatus for laser dicing 审中-公开
公开(公告)号：US20050221586A1
公开(公告)日：2005-10-06
申请号：US11145367
申请日：2005-06-03
申请人： Rose Mulligan , Sujit Sharan
发明人： Rose Mulligan , Sujit Sharan
IPC分类号： B23K26/12 , B23K26/14 , H01L21/301 , H01L21/311 , H01L21/3213 , H01L21/46 , H01L21/78
CPC分类号： B23K26/123 , B23K26/12 , B23K26/127 , B23K26/348 , H01L21/31116 , H01L21/32136 , H01L21/78
摘要： An apparatus and method of dicing a microelectronic device wafer by laser ablating at least an interconnect layer portion of the microelectronic device wafer in the presence of an anion plasma, wherein the anion plasma reacts with debris from the laser ablation to form a reaction gas.

10. 发明授权

US06921708B1 Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean 失效
标题翻译：具有低电阻率触点的集成电路及其使用原位等离子体掺杂和清洁的形成
公开(公告)号：US06921708B1
公开(公告)日：2005-07-26
申请号：US09549214
申请日：2000-04-13
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L21/285 , H01L21/306 , H01L21/768 , H01L23/485 , H01L21/26
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/76814 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or more than completely offset any loss of dopant due to the hot hydrogen clean. A protective conductive layer such as a metal silicide is then formed over the contact area in situ. The resulting integrated circuit has contacts with interfaces such as a silicide interfaces to contact areas having a particularly favorable dopant profile and concentration adjacent the silicide interfaces.
摘要翻译：接触孔底部包括掺杂半导体材料的接触区域在热氢等离子体中进行清洗，并在热氢清洗期间和/或与热氢清洗器分开暴露于包含与半导体材料相同的掺杂物质的等离子体中，，完全或更多地完全抵消由于热氢清洁而导致的掺杂剂的任何损失。然后在接触区域上原位形成诸如金属硅化物的保护性导电层。所得到的集成电路具有与诸如硅化物界面的接口与具有特别有利的掺杂剂分布和邻近硅化物界面的浓度的接触区的接触。

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