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1. 发明申请

US20030199126A1 Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen 有权
标题翻译：通过注入氧气分离形成绝缘体上硅衬底的方法
公开(公告)号：US20030199126A1
公开(公告)日：2003-10-23
申请号：US10128794
申请日：2002-04-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jack O. Chu , Feng-Yi Huang , Steven J. Koester , Devendra K. Sadana
IPC分类号： H01L021/00 , H01L021/84 , H01L021/4763 , H01L021/44
CPC分类号： H01L21/76243 , Y10S438/966 , Y10S438/967
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.
摘要翻译：通过将氧注入到包含交替的Si和SiGe层的Si / SiGe多层异质结构中来提供制造高质量，基本上松弛的绝缘体上硅衬底的方法。具体地说，通过将氧离子注入到包括Si和SiGe的交替层的多层异质结构中，形成绝缘体上的高质量，轻松的SiGe。接下来，注入步骤，将含有注入的氧离子的多层异质结构退火，即加热，以便主要形成多层结构的Si层之一内的掩埋氧化物区域。

2. 发明申请

US20030087504A1 Active wafer cooling during damage engineering implant to enchance buried oxide formation in simox wafers 失效
标题翻译：在损伤工程植入期间激活晶片冷却，以增强simox晶圆中的掩埋氧化物形成
公开(公告)号：US20030087504A1
公开(公告)日：2003-05-08
申请号：US10011518
申请日：2001-11-05
发明人： Yuri Erokhin , Julian G. Blake
IPC分类号： H01L021/76
CPC分类号： H01L21/76243 , Y10S438/966
摘要： The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300null C. to 600null C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50null C. to 150null C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate. The annealing step can be performed in a third chamber or in either of the first or second chambers.
摘要翻译：本发明提供了在诸如硅晶片的半导体衬底中形成掩埋氧化物层（BOX）区的方法和系统。一方面，在本发明的方法中，将初始剂量的氧离子注入到衬底中，同时将衬底温度保持在约300℃至600℃的范围内。随后，第二剂量的氧离子为植入衬底中同时主动冷却衬底，以将衬底温度维持在约50℃至150℃的范围内。这些离子注入步骤之后是在含氧气氛中的退火步骤，以形成连续的BOX区域基质。在一个优选实施例中，初始离子注入步骤在包括用于加热衬底的器件的腔室中执行，而第二离子注入步骤在配备有用于主动冷却衬底的器件的单独室中执行。退火步骤可以在第三室或第一室或第二室中的任一个中进行。

3. 发明申请

US20020130325A1 Method of achieving higher inversion layer mobility in novel silicon carbide semiconductor devices 审中-公开
标题翻译：在新型碳化硅半导体器件中实现更高反型层迁移率的方法
公开(公告)号：US20020130325A1
公开(公告)日：2002-09-19
申请号：US10055378
申请日：2002-01-22
申请人： PHILIPS ELECTRONICS NORTH AMERICA CORPORATION
发明人： Dev Alok
IPC分类号： H01L031/0312
CPC分类号： H01L29/7802 , H01L21/02532 , H01L21/02667 , H01L21/0445 , H01L21/049 , H01L21/2022 , H01L29/1608 , H01L29/66068 , Y10S438/966 , Y10S438/969
摘要： The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required. The method includes the steps of: (a) amorphizing the silicon carbide in at least one region of a monocrystalline silicon carbide substrate by ion implantation; (b) removing at least an effective amount of the carbon resulting from amorphizing the silicon carbide with an etchant effective to selectively remove carbon from the amorphized silicon carbide to produce an amorphous silicon-rich region; and (c) forming an oxide on the etched surface to provide a device which has an oxide region on (1) either an amorphous silicon-rich region which is (i) predominantly or entirely amorphous silicon or (ii) a mixture of predominantly amorphous silicon in combination with minor amounts of amorphous silicon carbide and/or silicon dioxide or (2) a monocrystalline silicon region; wherein (1) or (2) is present on a region of a silicon carbide substrate, or (3) a region of a silicon carbide substrate.
摘要翻译：本发明提供了一种在碳化硅顶部生产高质量热生长氧化物的方法。通过在需要或需要氧化物形成的区域中选择性地除去碳化硅中的碳而获得高质量的氧化物。该方法包括以下步骤：（a）通过离子注入在单晶碳化硅衬底的至少一个区域中使碳化硅非晶化; （b）用蚀刻剂除去至少有效量的碳非晶化所产生的碳，以有选择地从非晶化碳化硅中除去碳以产生无定形富硅区; 和（c）在蚀刻表面上形成氧化物以提供在（1）无定形富硅区域上具有氧化物区域的器件，所述非晶硅富集区域是（i）主要或完全非晶硅或（ii）主要为非晶态的硅与少量非晶碳化硅和/或二氧化硅组合，或（2）单晶硅区; 其中（1）或（2）存在于碳化硅衬底的区域上，或（3）碳化硅衬底的区域。

4. 发明授权

US06232206B1 Method for forming electrostatic discharge (ESD) protection transistors 有权
标题翻译：形成静电放电（ESD）保护晶体管的方法
公开(公告)号：US06232206B1
公开(公告)日：2001-05-15
申请号：US09208409
申请日：1998-12-10
申请人： Tiao-Yuan Huang , Horng-Chih Lin
发明人： Tiao-Yuan Huang , Horng-Chih Lin
IPC分类号： H01L21425
CPC分类号： H01L27/0251 , Y10S438/966
摘要： A method is provided for selective oxidation on source/drain regions of transistors on an integrated circuit. The method includes the steps of a) incorporating a neutral species into first kind of the source/drain regions, and b) forming oxidation regions over the first kind of source/drain regions and second kind of the source/drain regions, wherein the oxidation regions over the second kind are thicker than the oxidation regions over the first kind.
摘要翻译：提供了一种用于在集成电路上的晶体管的源极/漏极区域上进行选择性氧化的方法。该方法包括以下步骤：a）将中性物质并入第一种源极/漏极区域，以及b）在第一种源极/漏极区域和第二种源极/漏极区域上形成氧化区域，其中氧化第二类的区域比第一类的氧化区域厚。

5. 发明授权

US6143624A Shallow trench isolation formation with spacer-assisted ion implantation 有权
标题翻译：浅沟槽隔离形成与间隔子辅助离子注入
公开(公告)号：US6143624A
公开(公告)日：2000-11-07
申请号：US172088
申请日：1998-10-14
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762
CPC分类号： H01L21/76235 , H01L21/76237 , Y10S438/966 , Y10S438/981
摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
摘要翻译：通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强硅的氧化速率，并因此增加在沟槽边缘处产生的氧化物的厚度。实施例包括掩蔽和蚀刻阻挡氮化物层，在对应于随后形成的沟槽边缘的衬底的部分上形成保护性间隔物，蚀刻沟槽，去除保护性间隔物，将先前被保护隔离层覆盖的衬底的离子注入杂质，然后生长氧化物衬垫。形成在沟槽边缘上的所得氧化物由于硅氧化速率的增强而变厚，从而避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

6. 发明授权

US5215934A Process for reducing program disturbance in EEPROM arrays 失效
标题翻译：减少EEPROM阵列中程序干扰的过程
公开(公告)号：US5215934A
公开(公告)日：1993-06-01
申请号：US455510
申请日：1989-12-21
申请人： Jyh-Cherng J. Tzeng
发明人： Jyh-Cherng J. Tzeng
IPC分类号： G11C17/00 , G11C16/04 , H01L21/28 , H01L21/316 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28211 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28273 , H01L21/31658 , H01L29/42368 , H01L29/4916 , H01L29/7885 , H01L21/31662 , Y10S148/117 , Y10S438/966
摘要： A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.
摘要翻译： EEPROM器件中的栅极氧化物在最接近漏极的沟道区域上被选择性地增厚的方法，以便在所选择的单元的编程期间损害擦除类型的行为。首先，在靠近所述漏极区域的通道的一部分中的晶格结构被有意地损坏以增强其中的随后的热氧化。接下来，通道被热氧化以形成器件的隧道氧化物。由于在漏极附近的通道部分造成的损坏，损坏区域上的隧道氧化物相对于通道的另一部分较厚。漏极附近的较厚的栅极氧化物会加速相邻存储单元的漏极干扰，同时加快了源擦除性能。

7. 发明授权

US4597164A Trench isolation process for integrated circuit devices 失效
标题翻译：集成电路器件的沟槽隔离工艺
公开(公告)号：US4597164A
公开(公告)日：1986-07-01
申请号：US646600
申请日：1984-08-31
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763 , H01L21/265
CPC分类号： H01L21/76202 , H01L21/762 , H01L21/76224 , H01L21/763 , Y10S148/082 , Y10S438/966
摘要： Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.
摘要翻译：在集成电路器件上的选定区域周围形成隔离沟槽，并且在围绕这样的沟槽的外延硅中形成高掺杂区域。然后该器件在低温下被氧化，并且高掺杂区域的差异氧化生长导致厚场氧化物在沟槽外部生长，而只有一薄层氧化物在所选择的区域上生长。

8. 发明授权

US08039359B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US08039359B2
公开(公告)日：2011-10-18
申请号：US12395076
申请日：2009-02-27
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L21/76 , H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

9. 发明授权

US08021989B2 Method for high topography patterning 有权
标题翻译：高地形图案的方法
公开(公告)号：US08021989B2
公开(公告)日：2011-09-20
申请号：US11441821
申请日：2006-05-26
申请人： Staf Verhaegen , Axel Nackaerts
发明人： Staf Verhaegen , Axel Nackaerts
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76281 , H01L29/66795 , H01L29/785 , Y10S438/966
摘要： One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.
摘要翻译：一个发明方面涉及一种用于隔离半导体材料的结构的方法，包括提供半导体材料的图案，所述图案包括至少一条提升的线，限定所述图案中的器件区域，所述器件区域至少包括所述至少一个升高的并且修改半导体材料在所述器件区域外部的导电性能，使得器件区域是电隔离的。

10. 发明授权

US07538395B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US07538395B2
公开(公告)日：2009-05-26
申请号：US11859570
申请日：2007-09-21
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L23/62 , G11C11/36 , H01L21/00
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

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