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1. 发明授权

US5623446A Semiconductor integrated circuit having a voltage booster and precharging circuit 失效
标题翻译：具有升压器和预充电电路的半导体集成电路
公开(公告)号：US5623446A
公开(公告)日：1997-04-22
申请号：US572380
申请日：1995-12-14
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/409 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is transferred, a transfer gate to connect the first bit line to the first node and the second bit line to the second node, a sense amplifier located between the first node and the second node, an equalizer for equalizing the first node and the second node located between the first node and the second node, a voltage booster for boosting the control signal for the transfer gate and the equalizer. In the DRAM, the control signals for the transmisiion gate and the equalizer are set at V.sub.CC during the precharge cycle, and boosted above V.sub.CC in the activation cycle after the precharge cycle, and the control signal for the transfer gate is changed to V.sub.CC and the control signal for the equalizer is changed to the ground potential V.sub.SS in synchronization with a selection of the word line.
摘要翻译：可在预充电周期和激活周期中操作的DRAM包括字线，其中包括第一位线和第二位线的位线，位于第一位线和第二位线之间的存储器单元，第一节点和传送存储器单元中的数据的第二节点，将第一位线连接到第一节点的传输门和到第二节点的第二位线;位于第一节点和第二节点之间的读出放大器，均衡器，用于均衡第一节点和位于第一节点和第二节点之间的第二节点;升压器，用于升压传输门和均衡器的控制信号。在DRAM中，在预充电周期期间，传输门和均衡器的控制信号被设置为VCC，并且在预充电周期之后在激活周期中升高到VCC以上，并且传输门的控制信号变为VCC，并且与字线的选择同步，均衡器的控制信号变为接地电位VSS。

2. 发明授权

US5914505A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5914505A
公开(公告)日：1999-06-22
申请号：US706394
申请日：1996-08-30
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/413 , G11C5/14 , G11C7/10 , G11C11/409 , H01L27/02 , H01L27/092 , H01L27/105 , H01L27/10
CPC分类号： G11C7/1078 , G11C5/14 , H01L27/0251 , H01L27/0928 , H01L27/105
摘要： A semiconductor integrated circuit includes an input circuit for receiving an input signal from the outside, an internal circuit connected to the input circuit, an output circuit connected to the internal circuit for outputting an output signal to the outside, a power supply line connected to each of the circuits, a power supply terminal connected to the power supply line, a first ground conductor connected to the input circuit, a second ground conductor separated from the first ground conductor and connected to the internal circuit, a first ground terminal connected to the first ground conductor and a second ground terminal connected to the second ground conductor. Because of the provision of the ground conductor exclusively for the input circuit, malfunction of the input circuit due to power supply fluctuations is prevented and an operation margin is increased.
摘要翻译：半导体集成电路包括用于从外部接收输入信号的输入电路，连接到输入电路的内部电路，连接到内部电路以将输出信号输出到外部的输出电路，连接到每一个的电源线连接到电源线的电源端子，连接到输入电路的第一接地导体，与第一接地导体分离并连接到内部电路的第二接地导体，连接到第一接地导体的第一接地端子接地导体和连接到第二接地导体的第二接地端子。由于专门为输入电路提供接地导体，所以防止了由于电源波动引起的输入电路的故障，并增加了操作余量。

3. 发明授权

US5734292A Intermediate potential generation circuit 失效
标题翻译：中间电位生成电路
公开(公告)号：US5734292A
公开(公告)日：1998-03-31
申请号：US520773
申请日：1995-08-30
申请人： Yutaka Shirai , Toshiki Hisada , Hiroyuki Koinuma
发明人： Yutaka Shirai , Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/407 , G05F3/24 , G11C5/14 , G11C11/4074 , G11C11/4094 , G05F1/10
CPC分类号： G11C11/4074 , G05F3/242 , G11C11/4094 , G11C5/147
摘要： The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.
摘要翻译： NMOS晶体管的栅极接收参考电位，源极连接到输出节点。负载元件设置在该晶体管的漏极和电源之间。第一和第二反相器电路顺序地反转NMOS晶体管的漏极电位并将其传送到PMOS晶体管的栅极。 PMOS晶体管的源极连接到电源，漏极连接到输出节点。当输出节点的电位变得低于参考电位时，PMOS晶体管被激活直到来自反相器电路的输出反转，从而以大的电流对输出节点充电。

4. 发明授权

US5654935A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5654935A
公开(公告)日：1997-08-05
申请号：US528700
申请日：1995-09-15
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/41 , G11C8/18 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C8/18
摘要： A semiconductor memory includes a plurality of memory cells aligned in rows and columns, a plurality of bit lines respectively connected to the columns of the plurality of memory cells, a plurality of switch circuits each having one end connected to a corresponding one of the plurality of bit lines, the plurality of switch circuits being selectively turned on in accordance with a column address signal input from an outside to identify each of the columns, a data line to which the other end of each of the plurality of switch circuits is commonly connected, a pulse generation circuit for detecting a change in level of the column address signal with respect to first and second circuit thresholds different from each other to generate a pulse signal, the first circuit threshold being used for detecting a change in address signal from one level to the other level, and the second circuit threshold being used for detecting a change in address signal from the other level to one level, and a data detection circuit, connected to the data line and controlled by the pulse signal generated in accordance with the pulse generation circuits, for amplifying a potential of the data line to detect data.
摘要翻译：一种半导体存储器包括以行和列排列的多个存储单元，分别连接到多个存储单元的列的多个位线，多个开关电路，每个开关电路的一端连接到多个存储单元所述多个开关电路根据从外部输入的列地址信号选择性地导通，以识别每个所述列，所述多个开关电路中的每一个的另一端共同连接的数据线，用于检测相对于彼此不同的第一和第二电路阈值的列地址信号的电平变化以产生脉冲信号的脉冲发生电路，所述第一电路阈值用于检测地址信号从一个电平变化到另一个电平，第二电路阈值被用于检测从另一个电平到一个电平的地址信号的变化，以及一个数据检测电路，连接到数据线并由根据脉冲发生电路产生的脉冲信号控制，用于放大数据线的电位以检测数据。

5. 发明授权

US5198999A Serial input/output semiconductor memory including an output data latch circuit 失效
标题翻译：串行输入/输出半导体存储器，包括输出数据锁存电路
公开(公告)号：US5198999A
公开(公告)日：1993-03-30
申请号：US754170
申请日：1991-09-04
申请人： Katsumi Abe , Kaoru Nakagawa , Hiroyuki Koinuma
发明人： Katsumi Abe , Kaoru Nakagawa , Hiroyuki Koinuma
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.
摘要翻译：半导体存储器具有响应于从控制时钟输入到n个1位移位寄存器级移位半个周期的时钟信号而控制的输出数据锁存电路。存储器件包括多个读取数据锁存电路，以及耦合到n个1位移位寄存器级和多个选择器或多路复用器电路的多个写或地址数据锁存电路。噪声滤波器插入到n个1位移位寄存器级的时钟输入供给路径中，但不插入到输出数据锁存电路的时钟输入供给路径中。

6. 发明授权

US4746824A High potential hold circuit 失效
标题翻译：高电位保持电路
公开(公告)号：US4746824A
公开(公告)日：1988-05-24
申请号：US921272
申请日：1986-10-21
申请人： Koichi Magome , Hiroyuki Koinuma , Haruki Toda
发明人： Koichi Magome , Hiroyuki Koinuma , Haruki Toda
IPC分类号： H03K19/094 , G11C5/14 , H03K5/02 , H03K17/06 , H03K17/687 , H03K19/003 , H03K19/096 , H03K5/13 , G11C27/02
CPC分类号： H03K19/096 , H03K19/00315
摘要： This invention provides a high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node; a discharge enhancement mode MOS transistor for discharging the potential of the high potential node, having one end connected to the ground potential, the other end connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between the high potential node and the high potential hold transistor; and charge-discharge means for charging and discharging a potential of a gate of the field relaxation transistor.
摘要翻译：本发明提供一种高电位保持电路，包括：高电位节点; 高电位保持增强模式MOS晶体管，用于通过在节点充电之后将高电位保持晶体管设置为不导通状态来保持高电位节点的电位，其一端连接到第一输入信号，另一端连接到高电位节点; 放电增强模式MOS晶体管，用于对高电位节点的电位进行放电，其一端连接到地电位，另一端连接到高电位节点，栅极连接到第二输入信号; 位于高电位节点和高电位保持晶体管之间的场弛豫增强模式MOS晶体管; 以及用于对场弛豫晶体管的栅极的电位进行充电和放电的充放电装置。

7. 发明授权

US6078636A Counter circuit and semiconductor memory having counter circuit as address counter circuit 失效
标题翻译：具有计数器电路的计数器电路和半导体存储器作为地址计数器电路
公开(公告)号：US6078636A
公开(公告)日：2000-06-20
申请号：US921539
申请日：1997-09-02
申请人： Yutaka Shirai , Hiroyuki Koinuma
发明人： Yutaka Shirai , Hiroyuki Koinuma
IPC分类号： G11C11/407 , G11C7/10 , G11C11/408 , H03K23/40 , G06M3/00
CPC分类号： G11C7/1018 , G11C7/1045
摘要： A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2.sup.n in both sequences. The burst length of the counter circuit may be changeable, and the counter circuit may output a signal indicating whether the count number has reached the burst length.
摘要翻译：可以在半导体集成电路上的计数器电路，其可应用于线性序列和交错序列，并且能够以两个序列设置1,2,4,8或2n的突发长度。计数器电路的突发长度可以是可变的，并且计数器电路可以输出指示计数数目是否已经达到突发长度的信号。

8. 发明授权

US5274592A Semiconductor integrated circuit device for high-speed transmission of data and for improving reliability of transfer transistor, applicable to DRAM with voltage-raised word lines 失效
标题翻译：半导体集成电路器件，用于高速传输数据和提高传输晶体管的可靠性，适用于具有升压字线的DRAM
公开(公告)号：US5274592A
公开(公告)日：1993-12-28
申请号：US805560
申请日：1991-12-13
申请人： Atsushi Sueoka , Katsushi Nagaba , Hiroyuki Koinuma
发明人： Atsushi Sueoka , Katsushi Nagaba , Hiroyuki Koinuma
IPC分类号： G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4076
摘要： A semiconductor integrated circuit device having a high-efficiency transfer gate and which is applicable to a DRAM which has voltage-raised word lines configured from a data retention node, a data line that is precharged to a required level, a MOS transistor with the source and the drain each connected to a data line and a data retention node, a sense amplifier that amplifies the data that has been transferred to the data line via this MOS transistor a step-up circuit that applies a voltage that is higher than the drain voltage when compared with an absolute value, to the gate of the MOS transistor, and a step-down circuit for reducing the absolute value of a gate voltage of the MOS transistor at the timing of activation of the sense amplifier.
摘要翻译：一种具有高效率传输门的半导体集成电路器件，其可应用于具有由数据保持节点配置的升压字线的DRAM，预充电至所需电平的数据线，具有源极的MOS晶体管和各自连接到数据线和数据保持节点的漏极，读出放大器，通过该MOS晶体管放大已经传送到数据线的数据，该升压电路施加高于漏极电压的电压与MOS晶体管的栅极相比，以及降压电路，用于在感测放大器的激活时刻降低MOS晶体管的栅极电压的绝对值。

9. 发明授权

US4833342A Reference potential generating circuit 失效
标题翻译：参考电位发生电路
公开(公告)号：US4833342A
公开(公告)日：1989-05-23
申请号：US192667
申请日：1988-05-10
申请人： Masakazu Kiryu , Hiroyuki Koinuma , Kiminobu Suzuki
发明人： Masakazu Kiryu , Hiroyuki Koinuma , Kiminobu Suzuki
IPC分类号： H01L27/04 , G05F3/24 , H01L21/822 , H01L27/06
CPC分类号： G05F3/247
摘要： A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.

10. 发明授权

US4678934A Flip-flop circuit 失效
标题翻译：触发电路
公开(公告)号：US4678934A
公开(公告)日：1987-07-07
申请号：US884629
申请日：1986-07-11
申请人： Koichi Magome , Haruki Toda , Hiroyuki Koinuma , Hiroshi Sahara , Kiminobu Suzuki , Shigeo Ohshima , Kenji Komatsu
发明人： Koichi Magome , Haruki Toda , Hiroyuki Koinuma , Hiroshi Sahara , Kiminobu Suzuki , Shigeo Ohshima , Kenji Komatsu
IPC分类号： G11C11/40 , G11C8/06 , H03K3/356 , H03K3/26 , G11C7/00 , H03K17/687 , H03K19/094
CPC分类号： H03K3/356026 , G11C8/06
摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.
摘要翻译：触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电，与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

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