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1. 发明授权

US11727964B2 Arithmetic operations in memory 有权
公开(公告)号：US11727964B2
公开(公告)日：2023-08-15
申请号：US17550708
申请日：2021-12-14
申请人： Micron Technology, Inc.
发明人： Vijay S. Ramesh
IPC分类号： G11C7/10 , G06F9/30 , G06F7/50 , G11C7/06 , G06F7/523 , G06F7/52
CPC分类号： G11C7/1018 , G06F7/50 , G06F7/52 , G06F7/523 , G06F9/3001 , G06F9/30025 , G11C7/06 , G11C7/1006 , G11C7/1051
摘要： Systems, apparatuses, and methods related to arithmetic operations in memory are described. The arithmetic operations may be performed using bit strings and within a memory array without transferring the bit strings to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings to be transferred from the memory array to the sensing circuitry. In addition to the arithmetic operations, the sensing circuitry can also perform a logical operation using the one or more bit strings.

2. 发明授权

US11675662B2 Extended error detection for a memory device 有权
公开(公告)号：US11675662B2
公开(公告)日：2023-06-13
申请号：US17348211
申请日：2021-06-15
申请人： Micron Technology, Inc.
发明人： Scott E. Schaefer , Jongtae Kwak , Aaron P. Boehm
IPC分类号： G06F11/10 , G11C7/10
CPC分类号： G06F11/1072 , G06F11/1012 , G06F11/1052 , G11C7/1018
摘要： Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

3. 发明授权

US10839884B2 Memory component with efficient write operations 有权
公开(公告)号：US10839884B2
公开(公告)日：2020-11-17
申请号：US16097579
申请日：2017-05-03
申请人： RAMBUS INC.
发明人： Frederick A. Ware , John Eric Linstadt , Brent Steven Haukness , Kenneth L. Wright , Thomas Vogelsang
IPC分类号： G11C11/24 , G11C11/403 , G11C11/4097 , G11C11/4096 , G11C8/08 , G11C7/10 , G11C7/18 , G11C5/02 , G11C11/408 , G06F12/06 , G11C11/406 , G11C11/409 , G11C11/4091
CPC分类号： G11C11/403 , G06F12/06 , G11C5/025 , G11C7/1018 , G11C7/1045 , G11C7/1096 , G11C7/18 , G11C8/08 , G11C11/408 , G11C11/409 , G11C11/4085 , G11C11/4096 , G11C11/4097 , G11C11/40618 , G11C11/4091
摘要： A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

4. 发明申请

US20190206476A1 POWER REDUCTION TECHNIQUE DURING READ/WRITE BURSTS 审中-公开
公开(公告)号：US20190206476A1
公开(公告)日：2019-07-04
申请号：US16193825
申请日：2018-11-16
申请人： Micron Technology, Inc.
发明人： Harish N. Venkata
IPC分类号： G11C11/4074 , G06F11/10 , G11C29/52 , G11C11/4096
CPC分类号： G11C11/4074 , G06F11/1068 , G11C7/1018 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C29/52 , G11C2029/0411 , H01L27/10897
摘要： A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

5. 发明申请

US20190012280A1 INTERFACE COMPONENTS 审中-公开
公开(公告)号：US20190012280A1
公开(公告)日：2019-01-10
申请号：US16110171
申请日：2018-08-23
申请人： Micron Technology, Inc.
发明人： Matthew D. Rowley , Peter R. Castro
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F3/06
CPC分类号： G06F13/1668 , G06F3/061 , G06F3/0619 , G06F3/0626 , G06F3/0635 , G06F3/0649 , G06F3/0658 , G06F3/0661 , G06F3/0683 , G06F12/0253 , G06F13/4068 , G06F13/4282 , G11C7/10 , G11C7/1006 , G11C7/1018 , G11C2207/107
摘要： In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

6. 发明授权

US09898204B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
公开(公告)号：US09898204B2
公开(公告)日：2018-02-20
申请号：US15599731
申请日：2017-05-19
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06 , G11C11/16 , G11C7/10 , G11C7/22 , G06F13/28 , G06F12/0879
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

7. 发明申请

US20170372758A1 LOW POWER MEMORY DEVICE 审中-公开
公开(公告)号：US20170372758A1
公开(公告)日：2017-12-28
申请号：US15497229
申请日：2017-04-26
申请人： Chih-Cheng Hsiao
发明人： Chih-Cheng Hsiao
IPC分类号： G11C7/10 , G11C8/12 , G11C8/14
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1018 , G11C8/12 , G11C8/14 , G11C11/418 , G11C11/419
摘要： A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

8. 发明授权

US09658780B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
公开(公告)号：US09658780B2
公开(公告)日：2017-05-23
申请号：US15213278
申请日：2016-07-18
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06 , G11C7/10 , G11C7/22 , G11C11/16 , G06F12/0879 , G06F13/28
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

9. 发明申请

US20160328152A1 MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE 有权
公开(公告)号：US20160328152A1
公开(公告)日：2016-11-10
申请号：US15213278
申请日：2016-07-18
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

10. 发明授权

US09373371B2 Dynamic burst length output control in a memory 有权
标题翻译：内存中的动态突发长度输出控制
公开(公告)号：US09373371B2
公开(公告)日：2016-06-21
申请号：US14530911
申请日：2014-11-03
申请人： Micron Technology, Inc.
发明人： Jongtae Kwak
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/106 , G11C7/1018 , G11C7/1066 , G11C7/222
摘要： A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.
摘要翻译：用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。

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