专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190206476A1 POWER REDUCTION TECHNIQUE DURING READ/WRITE BURSTS 审中-公开
公开(公告)号：US20190206476A1
公开(公告)日：2019-07-04
申请号：US16193825
申请日：2018-11-16
申请人： Micron Technology, Inc.
发明人： Harish N. Venkata
IPC分类号： G11C11/4074 , G06F11/10 , G11C29/52 , G11C11/4096
CPC分类号： G11C11/4074 , G06F11/1068 , G11C7/1018 , G11C7/1078 , G11C7/1096 , G11C11/4096 , G11C29/52 , G11C2029/0411 , H01L27/10897
摘要： A memory device may include one or more memory banks that store digital data. The memory device includes first tri-state driver circuitry that provides a first signal to a first data read/write (DRW) line coupled between write driver circuitry and one or more DQ pads. The first signal is indicative of either a high state or a medium state. The memory device includes second tri-state driver circuitry that provides a second signal to a second data read/write (DRW) line coupled between the write driver circuitry and the one or more DQ pads. The second signal is indicative of either a medium state or a low state. A voltage level of the medium state is between a voltage level of the high state and a voltage level of the low state.

2. 发明申请

US20190012280A1 INTERFACE COMPONENTS 审中-公开
公开(公告)号：US20190012280A1
公开(公告)日：2019-01-10
申请号：US16110171
申请日：2018-08-23
申请人： Micron Technology, Inc.
发明人： Matthew D. Rowley , Peter R. Castro
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F3/06
CPC分类号： G06F13/1668 , G06F3/061 , G06F3/0619 , G06F3/0626 , G06F3/0635 , G06F3/0649 , G06F3/0658 , G06F3/0661 , G06F3/0683 , G06F12/0253 , G06F13/4068 , G06F13/4282 , G11C7/10 , G11C7/1006 , G11C7/1018 , G11C2207/107
摘要： In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

3. 发明授权

US09898204B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
公开(公告)号：US09898204B2
公开(公告)日：2018-02-20
申请号：US15599731
申请日：2017-05-19
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06 , G11C11/16 , G11C7/10 , G11C7/22 , G06F13/28 , G06F12/0879
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

4. 发明申请

US20170372758A1 LOW POWER MEMORY DEVICE 审中-公开
公开(公告)号：US20170372758A1
公开(公告)日：2017-12-28
申请号：US15497229
申请日：2017-04-26
申请人： Chih-Cheng Hsiao
发明人： Chih-Cheng Hsiao
IPC分类号： G11C7/10 , G11C8/12 , G11C8/14
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1018 , G11C8/12 , G11C8/14 , G11C11/418 , G11C11/419
摘要： A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

5. 发明授权

US09658780B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
公开(公告)号：US09658780B2
公开(公告)日：2017-05-23
申请号：US15213278
申请日：2016-07-18
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06 , G11C7/10 , G11C7/22 , G11C11/16 , G06F12/0879 , G06F13/28
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

6. 发明申请

US20160328152A1 MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE 有权
公开(公告)号：US20160328152A1
公开(公告)日：2016-11-10
申请号：US15213278
申请日：2016-07-18
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/1009 , G11C7/1018 , G11C7/22 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

7. 发明授权

US09373371B2 Dynamic burst length output control in a memory 有权
标题翻译：内存中的动态突发长度输出控制
公开(公告)号：US09373371B2
公开(公告)日：2016-06-21
申请号：US14530911
申请日：2014-11-03
申请人： Micron Technology, Inc.
发明人： Jongtae Kwak
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/106 , G11C7/1018 , G11C7/1066 , G11C7/222
摘要： A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.
摘要翻译：用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。

8. 发明申请

US20160005484A1 FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：US20160005484A1
公开(公告)日：2016-01-07
申请号：US14856261
申请日：2015-09-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
IPC分类号： G11C16/26 , G11C16/32 , G11C16/08
CPC分类号： G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
摘要： A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

9. 发明申请

US20160005482A1 FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：US20160005482A1
公开(公告)日：2016-01-07
申请号：US14856182
申请日：2015-09-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： KYEONG-HAN LEE , Seok-Cheon Kwon , Dong-Yang Lee
IPC分类号： G11C16/26 , G11C16/08 , G11C16/32
CPC分类号： G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
摘要： A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

10. 发明申请

US20150255133A1 ASSISTED LOCAL SOURCE LINE 有权
标题翻译：辅助本地源线
公开(公告)号：US20150255133A1
公开(公告)日：2015-09-10
申请号：US14495123
申请日：2014-09-24
申请人： Everspin Technologies, Inc.
发明人： Thomas Andre
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G06F12/0806 , G06F12/0879 , G06F2212/62 , G11C7/1018 , G11C7/1045 , G11C7/12 , G11C7/22 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/4091 , G11C11/4094 , G11C11/419 , G11C11/5607 , Y02D10/13
摘要： In some examples, a memory device has a memory array configured to include sets of bit cells grouped based in part on an arrangement of local source lines. Each of the groups of cells may include an assist bit having a lower impedance than the other bit cells of the group to cause current distributed by the local source lines to be largely provided to the assist bit. In some examples, the assist bit include a shorted tunnel junction and in other examples, multiple assist bits may be connected by one or more bridge assisted bit lines.
摘要翻译：在一些示例中，存储器件具有被配置为包括部分地基于本地源极线的布置分组的位单元的集合的存储器阵列。每个单元组可以包括具有比该组的其他位单元更低的阻抗的辅助位，以使得由本地源极线分配的电流大部分被提供给辅助位。在一些示例中，辅助位包括短路隧道结，并且在其他示例中，多个辅助位可以由一个或多个桥接辅助位线连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式