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1. 发明授权

US5274592A Semiconductor integrated circuit device for high-speed transmission of data and for improving reliability of transfer transistor, applicable to DRAM with voltage-raised word lines 失效
标题翻译：半导体集成电路器件，用于高速传输数据和提高传输晶体管的可靠性，适用于具有升压字线的DRAM
公开(公告)号：US5274592A
公开(公告)日：1993-12-28
申请号：US805560
申请日：1991-12-13
申请人： Atsushi Sueoka , Katsushi Nagaba , Hiroyuki Koinuma
发明人： Atsushi Sueoka , Katsushi Nagaba , Hiroyuki Koinuma
IPC分类号： G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4076
摘要： A semiconductor integrated circuit device having a high-efficiency transfer gate and which is applicable to a DRAM which has voltage-raised word lines configured from a data retention node, a data line that is precharged to a required level, a MOS transistor with the source and the drain each connected to a data line and a data retention node, a sense amplifier that amplifies the data that has been transferred to the data line via this MOS transistor a step-up circuit that applies a voltage that is higher than the drain voltage when compared with an absolute value, to the gate of the MOS transistor, and a step-down circuit for reducing the absolute value of a gate voltage of the MOS transistor at the timing of activation of the sense amplifier.
摘要翻译：一种具有高效率传输门的半导体集成电路器件，其可应用于具有由数据保持节点配置的升压字线的DRAM，预充电至所需电平的数据线，具有源极的MOS晶体管和各自连接到数据线和数据保持节点的漏极，读出放大器，通过该MOS晶体管放大已经传送到数据线的数据，该升压电路施加高于漏极电压的电压与MOS晶体管的栅极相比，以及降压电路，用于在感测放大器的激活时刻降低MOS晶体管的栅极电压的绝对值。

2. 发明授权

US5724281A Semiconductor integrated circuit having improved wiring in input terminal 失效
标题翻译：输入端子具有改进布线的半导体集成电路
公开(公告)号：US5724281A
公开(公告)日：1998-03-03
申请号：US790466
申请日：1997-01-29
申请人： Katsushi Nagaba
发明人： Katsushi Nagaba
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/10
摘要： The input pads DQ0 to DQ3 and the input buffers DIB0 to DIB3 are connected to each other by means of the wires La or Lb. In the case where the memory cell array is of the .times.4 bit pattern, the input pads DQ0 to DQ3 are connected to the input terminals of the input buffers DIB0 to DIB3, respectively, via the wires La, whereas in the case where the memory cell array is of the .times.1 bit pattern, one of the input pads, that is, DQ0 is connected to each of the input terminals of the input buffers DIB0 to DIB3 via the wires Lb. The structures from the input buffers DIB0 to DIB3 to the memory cell arrays are the same and common to the .times.4 bit pattern and the .times.1 bit pattern, and therefore an increase in the driving performance of the transistors in the input buffers DIB0 to DIB3 can be suppressed.
摘要翻译：输入焊盘DQ0至DQ3和输入缓冲器DIB0至DIB3通过电线La或Lb相互连接。在存储单元阵列为x4位模式的情况下，输入焊盘DQ0〜DQ3经由布线La分别与输入缓冲器DIB0〜DIB3的输入端子连接，而在存储单元阵列是x1位模式，其中一个输入焊盘，即DQ0经由电线Lb连接到输入缓冲器DIB0至DIB3的每个输入端。从输入缓冲器DIB0至DIB3到存储单元阵列的结构与x4位模式和x1位模式相同且相同，因此输入缓冲器DIB0至DIB3中的晶体管的驱动性能可以是被压制

3. 发明授权

US06226204B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06226204B1
公开(公告)日：2001-05-01
申请号：US09141450
申请日：1998-08-27
申请人： Kazuko Inuzuka , Katsushi Nagaba , Shigeo Ohshima
发明人： Kazuko Inuzuka , Katsushi Nagaba , Shigeo Ohshima
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： The data output circuit in a clock synchronous DRAM comprises a first data transfer circuit to which the data read from a memory is input and which transfers the input data to the output side in synchronization with an internal clock, an equalizing circuit to which the output of the first data transfer circuit is input during a read operation by a burst operation and to which high-impedance data is input after the read operation, a second data transfer circuit connected to the equalizing circuit, and an output buffer to which the output of the second data transfer circuit is input. The second data transfer circuit transfers all the data to the output buffer in synchronization with an output clock. This eliminates the dependence of the data access time and data hold time on data item and/or cycle and facilitates the timing control of the output control signal.
摘要翻译：时钟同步DRAM中的数据输出电路包括第一数据传输电路，从存储器读取的数据被输入到该第一数据传输电路，并且将输入数据与内部时钟同步地传送到输出端;均衡电路，第一数据传送电路在读操作期间通过脉冲串操作输入，并且在读操作之后输入高阻数据，连接到均衡电路的第二数据传输电路和输出缓冲器第二数据传输电路被输入。第二数据传输电路与输出时钟同步地将所有数据传送到输出缓冲器。这消除了数据访问时间和数据保持时间对数据项和/或周期的依赖性，并且便于输出控制信号的定时控制。

4. 发明授权

US5777946A Semiconductor memory circuit equipped with a column addressing circuit having a shift register 失效
标题翻译：配备有具有移位寄存器的列寻址电路的半导体存储器电路
公开(公告)号：US5777946A
公开(公告)日：1998-07-07
申请号：US770404
申请日：1996-12-20
申请人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
发明人： Kazuko Inuzuka , Shigeo Ohshima , Katsushi Nagaba
IPC分类号： G11C11/407 , G11C8/04 , G11C11/408
CPC分类号： G11C8/04
摘要： The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.
摘要翻译：本发明提供一种能够通过简化的高速寻址电路高速访问预定列部分的半导体存储器电路。 DRAM中的存储器电路使得通常包括计数器的列寻址电路的一部分在列地址缓冲器的前级构成列寻址电路中的移位寄存器，从而实现多个地址信号包装以进行访问预定列部分。

5. 发明授权

US5841730A Semiconductor memory device having synchronous write driver circuit 失效
标题翻译：具有同步写入驱动电路的半导体存储器件
公开(公告)号：US5841730A
公开(公告)日：1998-11-24
申请号：US790907
申请日：1997-01-29
申请人： Yasuyuki Kai , Katsushi Nagaba , Shigeo Ohshima
发明人： Yasuyuki Kai , Katsushi Nagaba , Shigeo Ohshima
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1078
摘要： A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.
摘要翻译：一种半导体存储器件，其能够在模式已经从写入模式改变为读取模式之后在第一读取周期中缩短数据读取时间，同时在尽可能简单的结构写入数据时保持高速循环时间，半导体存储器件具有存储单元阵列，具有可以写入数据的多个动态存储器单元，从存储单元读取数据的数据线对和必须写入存储单元的数据被传送到其上，用于驱动数据线的写入驱动器当数据被写入存储单元时，根据从外部提供的写入数据成对，以及均衡电路，用于每当数据线对由写入驱动器操作时将数据线对设置为中间电位。

6. 发明授权

US4907200A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US4907200A
公开(公告)日：1990-03-06
申请号：US264246
申请日：1988-10-27
申请人： Tatsuo Ikawa , Katsushi Nagaba
发明人： Tatsuo Ikawa , Katsushi Nagaba
IPC分类号： G11C11/401 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/4094 , G11C11/4085
摘要： A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.
摘要翻译：具有位线对的动态存储器。读取放大器连接在每对位线之间，用于从这些位线之间的电位差检测数据。存储器还包括第一和第二对伪字线。一方面，电容器耦合在每对位线中的第一位和第一对虚拟字线之间。类似地，电容器一方面耦合在每对位线中的第二位和第二对伪字线之间。第一虚拟字线驱动器连接到第一对虚拟字线对，用于在每对位线中的第一对中产生参考电位。第二虚拟字线驱动器连接到第二对伪字线对，用于在每对位线中的第二对中产生参考电位。存储器还具有用于选择第一或第二虚拟字线驱动器的选择电路。在预充电期间，虚拟字线驱动器将两对虚拟字线设置为预充电电位。在数据读取期间，由选择电路选择的虚拟字线驱动器将虚拟字线分别设定为高电位和低电位，由选择电路选择的虚拟字线驱动器将两个虚拟字线设为预充电潜力。

7. 发明授权

US4860327A Latch circuit constructed with MOS transistors and shift register using the latch circuits 失效
标题翻译：使用MOS晶体管构成的锁存电路和使用锁存电路的移位寄存器
公开(公告)号：US4860327A
公开(公告)日：1989-08-22
申请号：US201187
申请日：1988-06-02
申请人： Kaoru Nakagawa , Katsushi Nagaba
发明人： Kaoru Nakagawa , Katsushi Nagaba
IPC分类号： G11C11/409 , G11C19/28 , H03K3/356
CPC分类号： G11C19/28 , H03K3/356104
摘要： A first circuit is made up of a first clocked inverter and a first modified clocked inverter. A second circuit is made up of a second clocked inverter and a second modified clocked inverter. The first circuit has substantially the same circuit arrangement as that of the second circuit. The first circuit operates in response of the output signal from the second circuit, and vice versa.

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