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1. 发明授权

US12149247B2 Frequency divider and memory device including the same 有权
公开(公告)号：US12149247B2
公开(公告)日：2024-11-19
申请号：US17932023
申请日：2022-09-14
申请人： Samsung Electronics Co., Ltd.
发明人： Jaewoo Lee , Yoo-Chang Sung , Jeongdon Ihm , Hojun Chang , Jinseok Heo
IPC分类号： H03K21/02 , G11C11/4076 , G11C11/4093 , H03K23/40 , G11C7/10 , G11C7/22
CPC分类号： H03K21/026 , G11C11/4076 , G11C11/4093 , H03K23/40 , G11C7/1093 , G11C7/222
摘要： Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

2. 发明申请

US20210409025A1 DUAL-EDGE AWARE CLOCK DIVIDER 有权
公开(公告)号：US20210409025A1
公开(公告)日：2021-12-30
申请号：US17468945
申请日：2021-09-08
申请人： QUALCOMM Incorporated
发明人： Kevin BOWLES , Vijay Kiran KALYANAM , Sindhuja SUNDARARAJAN
IPC分类号： H03K21/02 , H03K23/40 , H04B1/40
摘要： A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

3. 发明授权

US11070211B2 Event counter circuits using partitioned moving average determinations and related methods 有权
公开(公告)号：US11070211B2
公开(公告)日：2021-07-20
申请号：US16887560
申请日：2020-05-29
申请人： Syzexion Inc.
发明人： Gregory Michael Wright
IPC分类号： H03K21/00 , H03K23/40 , G06F11/34 , G06F11/30 , H03K23/00 , H03K21/40 , H03K21/10 , H03K23/54 , H03K21/02
摘要： An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

4. 发明授权

US10831250B2 In-circuit supply transient scope 有权
公开(公告)号：US10831250B2
公开(公告)日：2020-11-10
申请号：US15894820
申请日：2018-02-12
申请人： Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
发明人： Anatoly Gelman
IPC分类号： G06F1/28 , G11C5/14 , G11C8/04 , H03K23/40 , G11C7/22
摘要： Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.

5. 发明授权

US10684797B2 Command-in-pipeline counter for a memory device 有权
公开(公告)号：US10684797B2
公开(公告)日：2020-06-16
申请号：US16119766
申请日：2018-08-31
申请人： MICRON TECHNOLOGY, INC.
发明人： Vijayakrishna J. Vankayala
IPC分类号： G06F3/06 , G11C7/10 , G11C7/22 , H03K23/40 , H03K19/20
摘要： Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

6. 发明授权

US10396109B2 Local storage device in high flux semiconductor radiation detectors and methods of operating thereof 有权
公开(公告)号：US10396109B2
公开(公告)日：2019-08-27
申请号：US15095786
申请日：2016-04-11
申请人： REDLEN TECHNOLOGIES
发明人： Kris Iniewski , Glenn Bindley , Robert Crestani
IPC分类号： A61B6/00 , A61B6/03 , G01T1/24 , G01T1/29 , G06T1/60 , G01T1/166 , H03K23/40 , H03K5/135 , H01L27/146 , H03K19/177
摘要： A detector element circuit for a CT imaging system may include a plurality of sensors for detecting photons passing through an object and a first electronic component configured to determine an energy of photons detected by the plurality of sensors and generate photon count data, which may be a count of detected photons in one or more energy bins. The detector element circuit may further include a second electronic component configured to receive the photon count data from the first electronic component and is clocked at a first clock rate; a local memory storage configured to receive the photon count data from the second electronic component at the first clock rate and to output the photon count data at a second clock rate.

7. 发明授权

US09473146B2 Apparatuses and methods for low power counting circuits 有权
标题翻译：低功耗计数电路的设备和方法
公开(公告)号：US09473146B2
公开(公告)日：2016-10-18
申请号：US14613192
申请日：2015-02-03
申请人： MICRON TECHNOLOGY, INC.
发明人： Hiroki Fujisawa
IPC分类号： H03B19/00 , H03K23/40 , H03K21/02
CPC分类号： H03K23/40 , H03K21/026
摘要： Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. The apparatus may further include a counter coupled to the frequency divider and configured to receive the intermediate clock signal. The counter may further be configured to provide a plurality of timing signals based on the intermediate clock signal. The apparatus may further include a frequency multiplier including a plurality of logic gates. Each of the plurality of logic gates may be coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals.
摘要翻译：本文描述了用于低功率计数电路的装置和方法。示例性装置可以包括分频器，其被配置为接收输入时钟信号并且调整时钟信号的频率以提供中间时钟信号。该装置还可以包括耦合到分频器并被配置为接收中间时钟信号的计数器。计数器还可以被配置为基于中间时钟信号提供多个定时信号。该装置还可以包括包括多个逻辑门的倍频器。多个逻辑门中的每一个可以耦合到计数器并且被配置为接收多个定时信号的相应第一定时信号以及多个定时信号中的中间时钟信号或相应的第二定时信号中的至少一个。

8. 发明申请

US20160142058A1 DELAY CIRCUIT 有权
标题翻译：延时电路
公开(公告)号：US20160142058A1
公开(公告)日：2016-05-19
申请号：US14796933
申请日：2015-07-10
申请人： SK hynix Inc.
发明人： Yo-Sep LEE
IPC分类号： H03K23/40 , H03K5/135
CPC分类号： H03K5/135 , H03K23/66 , H03K2005/00241 , H03K2005/00293
摘要： A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.
摘要翻译：延迟电路可以包括适合于测量关于输入信号是否对应于基于时钟的偶数周期或奇数周期中的任一个的定时的精细定时信息的精细定时测量单元，适于延迟输入的粗延迟单元信号，其精细定时由精细定时测量单元与分频时钟同步并输出延迟信号，精度定时应用单元适用于将精细定时信息应用于粗延迟单元的延迟信号。

9. 发明申请

US20160056824A1 DIGITAL COUNTER 有权
标题翻译：数字计数器
公开(公告)号：US20160056824A1
公开(公告)日：2016-02-25
申请号：US14563525
申请日：2014-12-08
申请人： SK hynix Inc. , Industry-University Cooperation Foundation Hanyang University
发明人： Byong Deok CHOI , Jong Seok KIM , Don Ku LEE
IPC分类号： H03K23/40
CPC分类号： H03K23/40
摘要： A digital counter may include a first count unit suitable for outputting a first bit signal having a constant level in response to a first clock signal, a second count unit suitable for outputting a second bit signal having a constant level in response to a second clock signal, and a third count unit suitable for outputting a third bit signal toggling in response to the second clock signal, and performing a count operation.
摘要翻译：数字计数器可以包括适于输出响应于第一时钟信号具有恒定电平的第一位信号的第一计数单元，适于输出响应于第二时钟信号具有恒定电平的第二位信号的第二计数单元以及第三计数单元，其适于输出响应于所述第二时钟信号而切换的第三位信号，并且执行计数操作。

10. 发明申请

US20050232056A1 Electronic device with data storage device 审中-公开
标题翻译：带数据存储设备的电子设备
公开(公告)号：US20050232056A1
公开(公告)日：2005-10-20
申请号：US10525811
申请日：2003-07-31
申请人： Katarzyna Leijten-Nowak
发明人： Katarzyna Leijten-Nowak
IPC分类号： G11C8/04 , G11C19/00 , G11C19/28 , H03K3/356 , H03K19/173 , H03K23/40 , G11C8/00
CPC分类号： G11C8/04
摘要： An electronic device (100) has a data storage device (120) for storing N data elements, the data storage device (120) comprising a first collection (122) of data storage elements (130). The first collection (122) of data storage elements (130) is accessible through an address decoder (140). In a shift register mode of the data storage device (120), the address decoder (140) is responsive to an address generator (160) comprising a modulo-N counter. Rather than having to shift data elements from one data storage element (130) to another, the address generator (160) generates a pointer to the data storage element (130) that contains the data element that is to be shifted out of the shift register. This has the advantage that the output of a predecessor data storage element (130) in a shift register need not be interconnected to the input of its successor. In addition, the amount of data traffic required during a shift is drastically reduced. The invention is particularly relevant to reconfigurable logic devices that use look-up tables for implementing shift registers.
摘要翻译：电子设备（100）具有用于存储N个数据元素的数据存储设备（120），数据存储设备（120）包括数据存储元件（130）的第一集合（122）。数据存储元件（130）的第一集合（122）可通过地址解码器（140）访问。在数据存储设备（120）的移位寄存器模式中，地址解码器（140）响应包括模N计数器的地址生成器（160）。地址生成器（160）不是必须将数据元素从一个数据存储元件（130）移位到另一个数据存储元件（130）而产生指向数据存储元件（130）的指针，该指针包含要移出移位寄存器的数据元素。这具有以下优点：移位寄存器中的前导数据存储元件（130）的输出不需要与其后继者的输入互连。此外，班次期间所需的数据流量大幅减少。本发明与使用查找表来实现移位寄存器的可重构逻辑器件特别相关。

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