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1. 发明公开

US20240361795A1 VOLTAGE REFERENCE CIRCUIT AND METHOD FOR PROVIDING REFERENCE VOLTAGE 审中-公开
公开(公告)号：US20240361795A1
公开(公告)日：2024-10-31
申请号：US18765706
申请日：2024-07-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yen-Ting WANG , Alan ROTH , Eric SOENEN , Alexander KALNITSKY , Liang-Tai KUO , Hsin-Li CHENG
IPC分类号： G05F3/26 , G05F3/24
CPC分类号： G05F3/262 , G05F3/24 , G05F3/247
摘要： Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor. A bulk and a source of the flipped-gate transistor are coupled to a ground. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

2. 发明申请

US20180136681A1 VOLTAGE REFERENCE BUFFER CIRCUIT 审中-公开
公开(公告)号：US20180136681A1
公开(公告)日：2018-05-17
申请号：US15800935
申请日：2017-11-01
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHE-WEI CHANG , KAI-YIN LIU , LIANG-HUAN LEI , SHIH-HSIUNG HUANG
IPC分类号： G05F1/618 , G05F3/24 , G05F1/40 , G05F1/571 , G05F1/573 , G05F1/575
CPC分类号： G05F1/618 , G05F1/40 , G05F1/571 , G05F1/573 , G05F1/575 , G05F3/247
摘要： The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.

3. 发明授权

US09710007B2 Integrated circuit capable of providing a stable reference current and an electronic device with the same 有权
公开(公告)号：US09710007B2
公开(公告)日：2017-07-18
申请号：US14930202
申请日：2015-11-02
申请人： ALi Corporation
发明人： Hsu-Che Nee , Liang-Hsin Chen , Yi-Hsien Cheng
IPC分类号： G05F3/24 , G05F3/26 , H03G1/00 , H03F1/30 , H03G3/12
CPC分类号： G05F3/245 , G05F3/247 , G05F3/262 , H03F1/30 , H03G1/0017 , H03G3/12
摘要： An electronic device and an integrated circuit thereof are provided. The integrated circuit includes a voltage generator and a current generator with a negative temperature coefficient. The voltage generator generates a reference voltage proportional to an absolute temperature based on a predetermined value. The current generator with the negative temperature coefficient receives the reference voltage and generates a reference current based on the reference voltage.

4. 发明授权

US09331568B2 Method and apparatus for load switch controller with tracking to support DDR termination 有权
标题翻译：负载开关控制器的方法和装置，具有跟踪支持DDR终止
公开(公告)号：US09331568B2
公开(公告)日：2016-05-03
申请号：US13834052
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Crown Sen Shieh , Abid Hussain
IPC分类号： G06F1/26 , H02M3/04 , G05F3/24
CPC分类号： H02M3/04 , G05F3/247 , G06F1/26 , Y10T307/406
摘要： A power control device can generate control signals to control operation of power sources. At least one of the control signals may be referenced to an internally provided reference voltage or an externally provided reference voltage. Additional control signals control operation of load switches that can be connected to the power sources to provide secondary sources of power. The load switches can be turned in a gradual manner at rates that depend on the power sources to which they are connected. The outputs of the load switches can be monitored for overvoltage and undervoltage conditions relative to the power sources to which they are connected.
摘要翻译：功率控制装置可以产生控制信号以控制电源的操作。至少一个控制信号可以参考内部提供的参考电压或外部提供的参考电压。附加的控制信号控制可连接到电源的负载开关的操作，以提供二次电源。负载开关可以以依赖于它们连接的电源的速率逐渐地转动。负载开关的输出可以相对于与它们连接的电源进行过压和欠压条件的监控。

5. 发明授权

US09170596B2 Integrated circuits having cascode transistor 有权
标题翻译：具有共源共栅晶体管的集成电路
公开(公告)号：US09170596B2
公开(公告)日：2015-10-27
申请号：US14301409
申请日：2014-06-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yvonne Lin
IPC分类号： G05F1/10 , H03K3/01 , G05F3/24 , H01L25/03
CPC分类号： G05F3/247 , G05F3/30 , H01L25/03 , H01L2924/0002 , H03F1/223 , H01L2924/00
摘要： An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.
摘要翻译：集成电路包括第一电路。第一电路包括具有第一掺杂剂类型的第一晶体管。第一电路还包括具有第一掺杂剂类型的第一共源共栅晶体管，其中与第一晶体管串联连接的第一共源共栅晶体管。第一电路还包括具有与第一掺杂剂类型相反的第二掺杂剂类型的第二晶体管，其中第二晶体管与第一晶体管串联连接。第一电路包括具有第二掺杂剂类型的第二共源共栅晶体管，其中第二共源共栅晶体管与第二晶体管串联连接。集成电路还包括被配置为调节第一共源共栅晶体管或第二共源共栅晶体管中的至少一个的阈值电压的第一偏置电路。

6. 发明申请

US20130241285A1 METHOD AND APPARATUS FOR LOAD SWITCH CONTROLLER WITH TRACKING TO SUPPORT DDR TERMINATION 有权
标题翻译：负载开关控制器跟踪支持DDR终止的方法和装置
公开(公告)号：US20130241285A1
公开(公告)日：2013-09-19
申请号：US13834052
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Crown Sen Shieh , Abid Hussain
IPC分类号： H02M3/04
CPC分类号： H02M3/04 , G05F3/247 , G06F1/26 , Y10T307/406
摘要： A power control device can generate control signals to control operation of power sources. At least one of the control signals may be referenced to an internally provided reference voltage or an externally provided reference voltage. Additional control signals control operation of load switches that can be connected to the power sources to provide secondary sources of power. The load switches can be turned in a gradual manner at rates that depend on the power sources to which they are connected. The outputs of the load switches can be monitored for overvoltage and undervoltage conditions relative to the power sources to which they are connected.
摘要翻译：功率控制装置可以产生控制信号以控制电源的操作。至少一个控制信号可以参考内部提供的参考电压或外部提供的参考电压。附加的控制信号控制可连接到电源的负载开关的操作，以提供二次电源。负载开关可以以依赖于它们连接的电源的速率逐渐地转动。负载开关的输出可以相对于与它们连接的电源进行过压和欠压条件的监控。

7. 发明申请

US20090295466A1 METHOD TO REDUCE VARIATION IN CMOS DELAY 有权
标题翻译：降低CMOS延迟变化的方法
公开(公告)号：US20090295466A1
公开(公告)日：2009-12-03
申请号：US12129683
申请日：2008-05-30
申请人： Phat Truong , Jon Nguyen
发明人： Phat Truong , Jon Nguyen
IPC分类号： G05F1/10
CPC分类号： G05F3/247
摘要： Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.
摘要翻译：提出了用于补偿由电源，温度和工艺变化引起的集成电路性能变化的控制电压电路。控制电压电路包括串联连接的几个MOSFET晶体管，单位增益运算放大器和具有输入端子和输出端子的恒流源。第一MOSFET的输入源极端子连接到恒流源和单位增益运算放大器。电路的输出端子连接到CMOS延迟块。为了补偿性能变化，单位增益运算放大器之前或之前的输出电压节点随着运行过程状态变慢或温度升高而偏移。相反，当过程变得更快或者温度降低时，输出电压节点移动较低。

8. 发明申请

US20050088152A1 Regulator circuitry and method 失效
标题翻译：调节器电路和方法
公开(公告)号：US20050088152A1
公开(公告)日：2005-04-28
申请号：US10695294
申请日：2003-10-27
申请人： David McClure , Mehdi Zamanian
发明人： David McClure , Mehdi Zamanian
IPC分类号： G05F1/40 , G05F3/24
CPC分类号： G05F3/247 , Y10T307/615 , Y10T307/696
摘要： A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.
摘要翻译：公开了一种用于系统的调节器电路和方法。调节器电路可以包括用于将第一电源电压与预定电压电平进行比较并基于该比较产生使能信号的比较电路。当由比较电路使能时，有选择地使能的电压调节器适于使得在调节电压下可用的预定电流电平。禁用时，电压调节器电路禁止提供电流。电压调节器可以包括通常在饱和运行模式下被偏置并由使能信号禁用的输出晶体管。通过基于比较电路的输出控制输出晶体管，消除了用于连接到第一电源电压的相对大的晶体管的需要。

9. 发明授权

US06822470B2 On-chip substrate regulator test mode 失效
公开(公告)号：US06822470B2
公开(公告)日：2004-11-23
申请号：US09935232
申请日：2001-08-22
申请人： Gary Gilliam
发明人： Gary Gilliam
IPC分类号： G01R3128
CPC分类号： G05F3/247 , G05F3/205
摘要： An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes-wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination.

10. 发明授权

US06806764B2 Reference voltage generation circuit 失效
标题翻译：参考电压发生电路
公开(公告)号：US06806764B2
公开(公告)日：2004-10-19
申请号：US10307446
申请日：2002-12-02
申请人： Yoshitsugu Inagaki , Koji Oka
发明人： Yoshitsugu Inagaki , Koji Oka
IPC分类号： G05F110
CPC分类号： G05F3/242 , G05F3/247
摘要： A start-up section is made up of an input transistor configured to receive at its gate a voltage at a node which varies with the magnitude of a current flowing in one branch of a current mirror in a reference voltage generation section, an inverter for reversing a drain voltage of the input transistor, an output transistor for supplying a start-up current to the reference voltage generation section in response to an output voltage from the inverter, and a current limit transistor serially connected to the input transistor. The current limit transistor receives a reduced gate-source voltage from the reference voltage generation section for limiting a flow of current in the input transistor upon completion of restarting the reference voltage generation section.
摘要翻译：启动部分由输入晶体管构成，该晶体管被配置为在其栅极处接收随着在参考电压产生部分中的电流镜的一个分支中流动的电流的大小而变化的节点的电压，用于反转的逆变器输入晶体管的漏极电压，用于响应于来自反相器的输出电压而向基准电压产生部分提供启动电流的输出晶体管，以及串联连接到输入晶体管的限流晶体管。电流限制晶体管从参考电压产生部分接收减小的栅极 - 源极电压，用于在重新启动参考电压产生部分时限制输入晶体管中的电流流动。

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