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1. 发明授权

US5623446A Semiconductor integrated circuit having a voltage booster and precharging circuit 失效
标题翻译：具有升压器和预充电电路的半导体集成电路
公开(公告)号：US5623446A
公开(公告)日：1997-04-22
申请号：US572380
申请日：1995-12-14
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/409 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A DRAM operable in a precharge cycle and an activation cycle, includes word lines, bit lines in which a first bit line and a second bit line are included, memory cells located between the first bit line and the second bit line, a first node and a second node through which data in the memory cell is transferred, a transfer gate to connect the first bit line to the first node and the second bit line to the second node, a sense amplifier located between the first node and the second node, an equalizer for equalizing the first node and the second node located between the first node and the second node, a voltage booster for boosting the control signal for the transfer gate and the equalizer. In the DRAM, the control signals for the transmisiion gate and the equalizer are set at V.sub.CC during the precharge cycle, and boosted above V.sub.CC in the activation cycle after the precharge cycle, and the control signal for the transfer gate is changed to V.sub.CC and the control signal for the equalizer is changed to the ground potential V.sub.SS in synchronization with a selection of the word line.
摘要翻译：可在预充电周期和激活周期中操作的DRAM包括字线，其中包括第一位线和第二位线的位线，位于第一位线和第二位线之间的存储器单元，第一节点和传送存储器单元中的数据的第二节点，将第一位线连接到第一节点的传输门和到第二节点的第二位线;位于第一节点和第二节点之间的读出放大器，均衡器，用于均衡第一节点和位于第一节点和第二节点之间的第二节点;升压器，用于升压传输门和均衡器的控制信号。在DRAM中，在预充电周期期间，传输门和均衡器的控制信号被设置为VCC，并且在预充电周期之后在激活周期中升高到VCC以上，并且传输门的控制信号变为VCC，并且与字线的选择同步，均衡器的控制信号变为接地电位VSS。

2. 发明授权

US5914505A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5914505A
公开(公告)日：1999-06-22
申请号：US706394
申请日：1996-08-30
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/413 , G11C5/14 , G11C7/10 , G11C11/409 , H01L27/02 , H01L27/092 , H01L27/105 , H01L27/10
CPC分类号： G11C7/1078 , G11C5/14 , H01L27/0251 , H01L27/0928 , H01L27/105
摘要： A semiconductor integrated circuit includes an input circuit for receiving an input signal from the outside, an internal circuit connected to the input circuit, an output circuit connected to the internal circuit for outputting an output signal to the outside, a power supply line connected to each of the circuits, a power supply terminal connected to the power supply line, a first ground conductor connected to the input circuit, a second ground conductor separated from the first ground conductor and connected to the internal circuit, a first ground terminal connected to the first ground conductor and a second ground terminal connected to the second ground conductor. Because of the provision of the ground conductor exclusively for the input circuit, malfunction of the input circuit due to power supply fluctuations is prevented and an operation margin is increased.
摘要翻译：半导体集成电路包括用于从外部接收输入信号的输入电路，连接到输入电路的内部电路，连接到内部电路以将输出信号输出到外部的输出电路，连接到每一个的电源线连接到电源线的电源端子，连接到输入电路的第一接地导体，与第一接地导体分离并连接到内部电路的第二接地导体，连接到第一接地导体的第一接地端子接地导体和连接到第二接地导体的第二接地端子。由于专门为输入电路提供接地导体，所以防止了由于电源波动引起的输入电路的故障，并增加了操作余量。

3. 发明授权

US5734292A Intermediate potential generation circuit 失效
标题翻译：中间电位生成电路
公开(公告)号：US5734292A
公开(公告)日：1998-03-31
申请号：US520773
申请日：1995-08-30
申请人： Yutaka Shirai , Toshiki Hisada , Hiroyuki Koinuma
发明人： Yutaka Shirai , Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/407 , G05F3/24 , G11C5/14 , G11C11/4074 , G11C11/4094 , G05F1/10
CPC分类号： G11C11/4074 , G05F3/242 , G11C11/4094 , G11C5/147
摘要： The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.
摘要翻译： NMOS晶体管的栅极接收参考电位，源极连接到输出节点。负载元件设置在该晶体管的漏极和电源之间。第一和第二反相器电路顺序地反转NMOS晶体管的漏极电位并将其传送到PMOS晶体管的栅极。 PMOS晶体管的源极连接到电源，漏极连接到输出节点。当输出节点的电位变得低于参考电位时，PMOS晶体管被激活直到来自反相器电路的输出反转，从而以大的电流对输出节点充电。

4. 发明授权

US5654935A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5654935A
公开(公告)日：1997-08-05
申请号：US528700
申请日：1995-09-15
申请人： Toshiki Hisada , Hiroyuki Koinuma
发明人： Toshiki Hisada , Hiroyuki Koinuma
IPC分类号： G11C11/41 , G11C8/18 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C8/18
摘要： A semiconductor memory includes a plurality of memory cells aligned in rows and columns, a plurality of bit lines respectively connected to the columns of the plurality of memory cells, a plurality of switch circuits each having one end connected to a corresponding one of the plurality of bit lines, the plurality of switch circuits being selectively turned on in accordance with a column address signal input from an outside to identify each of the columns, a data line to which the other end of each of the plurality of switch circuits is commonly connected, a pulse generation circuit for detecting a change in level of the column address signal with respect to first and second circuit thresholds different from each other to generate a pulse signal, the first circuit threshold being used for detecting a change in address signal from one level to the other level, and the second circuit threshold being used for detecting a change in address signal from the other level to one level, and a data detection circuit, connected to the data line and controlled by the pulse signal generated in accordance with the pulse generation circuits, for amplifying a potential of the data line to detect data.
摘要翻译：一种半导体存储器包括以行和列排列的多个存储单元，分别连接到多个存储单元的列的多个位线，多个开关电路，每个开关电路的一端连接到多个存储单元所述多个开关电路根据从外部输入的列地址信号选择性地导通，以识别每个所述列，所述多个开关电路中的每一个的另一端共同连接的数据线，用于检测相对于彼此不同的第一和第二电路阈值的列地址信号的电平变化以产生脉冲信号的脉冲发生电路，所述第一电路阈值用于检测地址信号从一个电平变化到另一个电平，第二电路阈值被用于检测从另一个电平到一个电平的地址信号的变化，以及一个数据检测电路，连接到数据线并由根据脉冲发生电路产生的脉冲信号控制，用于放大数据线的电位以检测数据。

5. 发明授权

US09129688B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US09129688B2
公开(公告)日：2015-09-08
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/16 , G11C16/04 , H01L27/115
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

6. 发明授权

US08630106B2 Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate 有权
标题翻译：具有各自包括电荷累积层和控制栅极的存储单元的半导体存储器件
公开(公告)号：US08630106B2
公开(公告)日：2014-01-14
申请号：US12695623
申请日：2010-01-28
申请人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
发明人： Takatoshi Minamoto , Toshiki Hisada , Dai Nakamura
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M
摘要翻译：半导体存储器件包括存储单元单元，字线，驱动电路和第一晶体管。字线连接到第0至第N个存储单元的控制栅极。第（N + 1）个第一晶体管的数量分别将电压转移到字线。将电压转移到第i个（i是0到N的范围内的自然数）字线的第一晶体管中的一个以上，靠近第i个字线的字线的M（M

7. 发明授权

US08243491B2 Semiconductor integrated circuit including semiconductor memory 失效
标题翻译：半导体集成电路包括半导体存储器
公开(公告)号：US08243491B2
公开(公告)日：2012-08-14
申请号：US12884378
申请日：2010-09-17
申请人： Toshiki Hisada , Hiromitsu Mashita
发明人： Toshiki Hisada , Hiromitsu Mashita
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C7/18 , G11C2207/002 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.
摘要翻译：根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。位线包括顺序排列的第一，第二，第三和第四位线。第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。

8. 发明申请

US20120001331A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120001331A1
公开(公告)日：2012-01-05
申请号：US13051652
申请日：2011-03-18
申请人： Takayuki Toba , Tohru Ozaki , Toshiki Hisada , Hiromitsu Mashita , Takafumi Taguchi
发明人： Takayuki Toba , Tohru Ozaki , Toshiki Hisada , Hiromitsu Mashita , Takafumi Taguchi
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L21/76816 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.
摘要翻译：根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。多个第一互连周期性地布置成在一个方向上延伸。第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。第三互连设置在组和第二互连之间。多个导电构件设置在从第二互连件观察的与组相反的一侧上。第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

9. 发明申请

US20130003461A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE 有权
标题翻译：可减少芯片尺寸的半导体存储器件
公开(公告)号：US20130003461A1
公开(公告)日：2013-01-03
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki ISOBE , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki ISOBE , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

10. 发明授权

US08243524B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08243524B2
公开(公告)日：2012-08-14
申请号：US12723864
申请日：2010-03-15
申请人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
发明人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C16/26 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526
摘要： A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.
摘要翻译：半导体存储装置具有读出放大器。读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连，并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上部互连件，并且连接到设置在所述第二上部互连件下方的所述虚拟接触互连件。

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