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1. 发明授权

US06525361B1 Process and integrated circuit for a multilevel memory cell with an asymmetric drain 有权
公开(公告)号：US06525361B1
公开(公告)日：2003-02-25
申请号：US09443964
申请日：1999-11-19
申请人： Tao Cheng Lu , Chung Ju Chen , Hon Sui Lin , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Chung Ju Chen , Hon Sui Lin , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： H01L27102
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5642 , G11C11/5692 , H01L27/112
摘要： An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

2. 发明授权

US06181604B2 Method for fast programming of EPROMS and multi-level flash EPROMS 有权
标题翻译： EPROMS和多级闪存EPROMS的快速编程方法
公开(公告)号：US06181604B2
公开(公告)日：2001-01-30
申请号：US09359073
申请日：1999-07-22
申请人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： G11C1606
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C16/0491 , G11C16/10 , G11C16/3418 , G11C2211/5621
摘要： A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.
摘要翻译：一种用于编程诸如EPROM或闪存EPROM的半导体存储器件的方法，其结合了降低源电压的优点和与增加栅极电压相关联的优点。编程周期分为程序禁止干扰期和程序周期。编程周期进一步分为子程序周期，每个子程序周期都有程序干扰和程序周期。字线WL电压可能随着每个子程序周期而增加，以提高编程速度。此外，程序干扰周期可以仅在第一子程序周期执行。每个子程序周期还可以包括验证周期，以便实现适合于编程多级闪存EPROMS的程序和验证技术。

3. 发明授权

US06175519B1 Virtual ground EPROM structure 有权
标题翻译：虚拟地EPROM结构
公开(公告)号：US06175519B1
公开(公告)日：2001-01-16
申请号：US09359197
申请日：1999-07-22
申请人： Tao Cheng Lu , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： G11C1606
CPC分类号： G11C16/0491 , G11C5/063
摘要： In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.
摘要翻译：在诸如EPROM或闪存EPROM的虚拟地面半导体存储器件中，程序干扰抑制单元可操作地连接到存储器阵列。存储器阵列包括多个金属虚拟接地和位线，其中至少两个位线选择晶体管连接到每个金属线。禁止的程序干扰连接到每个虚拟接地线和每个位线。在这种结构中，一个金属间距连接到两个掩埋的扩散线。程序禁止单元包括多个编程干扰禁止晶体管，其中每个晶体管连接在虚拟地和位线之间。连接DWL和DWR虚拟线以控制多个编程干扰被禁止的晶体管。通过将编程干扰抑制单元与存储器阵列组合，仅适用于MROM应用的常规阵列结构可以应用于EPROM或闪速EEPROM，从而可以减小单元大小。

4. 发明授权

US06204529B1 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate 有权
标题翻译： 8位每单元非易失性半导体存储器结构利用沟槽技术和介质浮栅
公开(公告)号：US06204529B1
公开(公告)日：2001-03-20
申请号：US09384482
申请日：1999-08-27
申请人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
发明人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923 , H01L29/7926
摘要： The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.
摘要翻译：本申请公开了一种用于存储多达8位信息的非易失性半导体存储器件。该器件具有一个导电类型的半导体衬底，半导体衬底的一部分的顶部上的中心底部扩散区域，在底部扩散区域的顶部上的第二半导体层，以及形成在第二半导体层中的左右扩散区域除了中心底部扩散区域，从而在右侧和中央底部扩散区域之间形成第一垂直通道。该器件还包括形成在半导体衬底，左，中，右底部扩散区和第二半导体层的暴露部分之上的俘获电介质层，以及形成在俘获电介质层上的字线。还公开了使用沟槽技术制造这种新型电池的方法。

5. 发明授权

US06215697B1 Multi-level memory cell device and method for self-converged programming 有权
标题翻译：用于自融合编程的多级存储单元器件和方法
公开(公告)号：US06215697B1
公开(公告)日：2001-04-10
申请号：US09231044
申请日：1999-01-14
申请人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
发明人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5625 , G11C2211/5634
摘要： A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell. The controller is also used to adjust voltages for both programming and read operations. The voltage difference resulting from the sources of the memory cell and reference cell is used to provide program control signals and thereby cease programming of the memory cell when convergence has been reached.
摘要翻译：一种用于自融合编程的多级存储单元设备和方法，其包括可切换地耦合到非可编程参考单元（或虚拟单元）的存储单元，所述单元布置在相应阵列中。电池的源节点和地之间的电流源电压与阈值电压相关，因此阈值电压增加，电流源电压降低。虚拟单元的阈值电压由稳定的电压源设定。对存储单元进行编程，并将存储单元的电流源电压与参考单元的电流源电压进行比较，因此可以使用电压差来检测编程单元的收敛与在参考细胞。参考单元和存储单元之间还包括控制器，用于根据浮动栅极存储单元的栅极耦合比来调整虚设单元的阈值电压。控制器也用于调节编程和读取操作的电压。由存储器单元和参考单元的源产生的电压差用于提供程序控制信号，从而在已经达到收敛时停止存储单元的编程。

6. 发明授权

US06432782B1 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate 有权
标题翻译： 8位每单元非易失性半导体存储器结构利用沟槽技术和介质浮栅
公开(公告)号：US06432782B1
公开(公告)日：2002-08-13
申请号：US09776290
申请日：2001-02-02
申请人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
发明人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923 , H01L29/7926
摘要： The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.
摘要翻译：本申请公开了一种用于存储多达8位信息的非易失性半导体存储器件。该器件具有一个导电类型的半导体衬底，半导体衬底的一部分的顶部上的中心底部扩散区域，在底部扩散区域的顶部上的第二半导体层，以及形成在第二半导体层中的左右扩散区域除了中心底部扩散区域，从而在右侧和中央底部扩散区域之间形成第一垂直通道。该器件还包括形成在半导体衬底，左，中，右底部扩散区和第二半导体层的暴露部分之上的俘获电介质层，以及形成在俘获电介质层上的字线。还公开了使用沟槽技术制造这种新型电池的方法。

7. 发明授权

US6046482A Cell structure for mask ROM 失效
标题翻译：掩模ROM的单元结构
公开(公告)号：US6046482A
公开(公告)日：2000-04-04
申请号：US935072
申请日：1997-09-25
申请人： Tao Cheng Lu , Mam-Tsung Wang
发明人： Tao Cheng Lu , Mam-Tsung Wang
IPC分类号： H01L21/8246 , H01L29/76
CPC分类号： H01L27/1124
摘要： A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.
摘要翻译：提出了一种没有ROM代码植入的掩模只读存储单元结构。通过使用双重多晶硅技术，存储数据“0”的ROM代码单元可以由具有双多晶硅层的单元和它们之间的绝缘层代替。具有双多晶硅层但在它们之间没有绝缘层的正电池形成正常电池存储数据“1”。根据本发明，掩模ROM的进一步缩放是可能的，并且由于高的结击穿电压可以释放操作条件。此外，双晶体技术使得冗余电路更容易实现。

8. 发明授权

US5895241A Method for fabricating a cell structure for mask ROM 失效
标题翻译：掩模ROM的单元结构的制造方法
公开(公告)号：US5895241A
公开(公告)日：1999-04-20
申请号：US825301
申请日：1997-03-28
申请人： Tao Cheng Lu , Mam-Tsung Wang
发明人： Tao Cheng Lu , Mam-Tsung Wang
IPC分类号： H01L21/8246
CPC分类号： H01L27/1124
摘要： A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.
摘要翻译：提出了一种没有ROM代码植入的掩模只读存储单元结构。通过使用双重多晶硅技术，存储数据“0”的ROM代码单元可以由具有双多晶硅层的单元和它们之间的绝缘层代替。具有双多晶硅层但在它们之间没有绝缘层的正电池形成正常电池存储数据“1”。根据本发明，掩模ROM的进一步缩放是可能的，并且由于高的结击穿电压可以释放操作条件。此外，双晶体技术使得冗余电路更容易实现。

9. 发明授权

US08501591B2 Method for manufacturing a multiple-bit-per-cell memory 有权
标题翻译：制造多位单元存储器的方法
公开(公告)号：US08501591B2
公开(公告)日：2013-08-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

10. 发明授权

US06996011B2 NAND-type non-volatile memory cell and method for operating same 有权
标题翻译： NAND型非易失性存储单元及其操作方法
公开(公告)号：US06996011B2
公开(公告)日：2006-02-07
申请号：US10855286
申请日：2004-05-26
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , H01L27/115
摘要： A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.
摘要翻译：由多个基本相同的EEPROM单元形成的NAND型可擦除可编程只读存储器（EEPROM）器件，每个EEPROM单元能够存储两位信息。用于操作存储器的简单方法包括擦除，编程和读取设备。

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