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1. 发明授权

US06175519B1 Virtual ground EPROM structure 有权
标题翻译：虚拟地EPROM结构
公开(公告)号：US06175519B1
公开(公告)日：2001-01-16
申请号：US09359197
申请日：1999-07-22
申请人： Tao Cheng Lu , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： G11C1606
CPC分类号： G11C16/0491 , G11C5/063
摘要： In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.
摘要翻译：在诸如EPROM或闪存EPROM的虚拟地面半导体存储器件中，程序干扰抑制单元可操作地连接到存储器阵列。存储器阵列包括多个金属虚拟接地和位线，其中至少两个位线选择晶体管连接到每个金属线。禁止的程序干扰连接到每个虚拟接地线和每个位线。在这种结构中，一个金属间距连接到两个掩埋的扩散线。程序禁止单元包括多个编程干扰禁止晶体管，其中每个晶体管连接在虚拟地和位线之间。连接DWL和DWR虚拟线以控制多个编程干扰被禁止的晶体管。通过将编程干扰抑制单元与存储器阵列组合，仅适用于MROM应用的常规阵列结构可以应用于EPROM或闪速EEPROM，从而可以减小单元大小。

2. 发明授权

US06525361B1 Process and integrated circuit for a multilevel memory cell with an asymmetric drain 有权
公开(公告)号：US06525361B1
公开(公告)日：2003-02-25
申请号：US09443964
申请日：1999-11-19
申请人： Tao Cheng Lu , Chung Ju Chen , Hon Sui Lin , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Chung Ju Chen , Hon Sui Lin , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： H01L27102
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5642 , G11C11/5692 , H01L27/112
摘要： An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

3. 发明授权

US06181604B2 Method for fast programming of EPROMS and multi-level flash EPROMS 有权
标题翻译： EPROMS和多级闪存EPROMS的快速编程方法
公开(公告)号：US06181604B2
公开(公告)日：2001-01-30
申请号：US09359073
申请日：1999-07-22
申请人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： G11C1606
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C16/0491 , G11C16/10 , G11C16/3418 , G11C2211/5621
摘要： A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.
摘要翻译：一种用于编程诸如EPROM或闪存EPROM的半导体存储器件的方法，其结合了降低源电压的优点和与增加栅极电压相关联的优点。编程周期分为程序禁止干扰期和程序周期。编程周期进一步分为子程序周期，每个子程序周期都有程序干扰和程序周期。字线WL电压可能随着每个子程序周期而增加，以提高编程速度。此外，程序干扰周期可以仅在第一子程序周期执行。每个子程序周期还可以包括验证周期，以便实现适合于编程多级闪存EPROMS的程序和验证技术。

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