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1. 发明授权

US07327611B2 Method and apparatus for operating charge trapping nonvolatile memory 有权
标题翻译：用于操作电荷捕获非易失性存储器的方法和装置
公开(公告)号：US07327611B2
公开(公告)日：2008-02-05
申请号：US11191367
申请日：2005-07-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/26
摘要： A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.
摘要翻译：具有电荷捕获结构的存储单元通过测量存储单元的衬底区域与存储单元的源极区域和存储器单元的漏极区域中的至少一个之间的电流来操作。当电荷捕获结构的其他部分存储不感兴趣的数据时，读取操作减小电荷俘获结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。通过增加存储单元上的净正电荷来擦除存储单元，并通过增加存储单元上的净负电荷进行编程。

2. 发明授权

US06721204B1 Memory erase method and device with optimal data retention for nonvolatile memory 有权
标题翻译：非易失性存储器的存储器擦除方法和具有最佳数据保留功能的器件
公开(公告)号：US06721204B1
公开(公告)日：2004-04-13
申请号：US10465395
申请日：2003-06-17
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1634
CPC分类号： G11C16/344
摘要： The invention advantageously provides a nonvolatile memory device and associated methods therefore, and, more particularly, an optimally designed nonvolatile memory device and methods therefor that advantageously prevent data loss in its trapping layer. A preferred embodiment of the method for operating a nonvolatile memory cell according to the invention advantageously comprises the steps of programming the memory cell, injecting electrons into a trapping layer of the memory cell from a semiconductor substrate, erasing the memory cell, detrapping the memory cell, and repeating the erasing and detrapping steps until a threshold voltage of the memory cell reaches a predetermined value. For the detrapping step, electrons can be detrapped from the trapping layer to a channel region of the memory cell, or to a gate of the memory cell. The method according to the invention can further include the steps of verifying the state of the trapping layer (high or low), and repeating the erasing and detrapping steps if the state of the trapping layer is not verified.
摘要翻译：本发明有利地提供了一种非易失性存储器件和相关联的方法，更具体地说，是一种最佳设计的非易失性存储器件及其方法，有利于防止其捕获层中的数据丢失。用于操作根据本发明的非易失性存储器单元的方法的优选实施例有利地包括以下步骤：对存储单元进行编程，将电子从半导体衬底注入到存储器单元的陷阱层中，擦除存储单元，去除存储单元，并且重复擦除和去除步骤，直到存储器单元的阈值电压达到预定值。对于去除步骤，电子可以从捕获层去除到存储器单元的通道区域或存储单元的栅极。根据本发明的方法还可以包括以下步骤：如果未验证捕获层的状态，则验证捕获层的状态（高或低），并重复擦除和去除步骤。

3. 发明授权

US07529128B2 Integrated code and data flash memory 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US07529128B2
公开(公告)日：2009-05-05
申请号：US11617613
申请日：2006-12-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

4. 发明授权

US07035147B2 Overerase protection of memory cells for nonvolatile memory 有权
标题翻译：对非易失性存储器的存储单元进行过度保护
公开(公告)号：US07035147B2
公开(公告)日：2006-04-25
申请号：US10465396
申请日：2003-06-17
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/344 , G11C16/0466 , G11C16/16 , G11C16/3445 , G11C16/3477
摘要： The invention provides a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a method for erasing a nonvolatile memory comprising a source, a gate, a drain, a channel and a trapping layer. The method according to a preferred embodiment of the invention generally comprises the steps of applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, applying a non-zero drain voltage to the drain in each erase shot wherein the drain voltage is generally higher in magnitude than the source voltage, generating hot holes in the nonvolatile memory, injecting the generated hot holes in the trapping layer near drain junction, and accordingly erasing the nonvolatile memory. The erase method according to a further embodiment of the invention comprises a verifying step after each erase shot for verifying the memory erase for the nonvolatile memory, and repeating the process steps according to the invention if the memory erase is not verified.
摘要翻译：本发明提供一种具有最佳存储器擦除功能的非易失性存储器和相应方法，更具体地说，涉及一种用于擦除包括源极，栅极，漏极，沟道和俘获层的非易失性存储器的方法。根据本发明的优选实施例的方法通常包括以下步骤：向栅极施加非零栅极电压，向源施加非零源电压，在每个擦除中向漏极施加非零漏极电压其中漏极电压的幅度通常大于源极电压，在非易失性存储器中产生热孔，在漏极结附近注入捕获层中产生的热孔，从而擦除非易失性存储器。根据本发明的另一实施例的擦除方法包括在用于验证非易失性存储器的存储器擦除的每个擦除镜头之后的验证步骤，并且如果未验证存储器擦除，则重复根据本发明的处理步骤。

5. 发明授权

US08501591B2 Method for manufacturing a multiple-bit-per-cell memory 有权
标题翻译：制造多位单元存储器的方法
公开(公告)号：US08501591B2
公开(公告)日：2013-08-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

6. 发明授权

US06996011B2 NAND-type non-volatile memory cell and method for operating same 有权
标题翻译： NAND型非易失性存储单元及其操作方法
公开(公告)号：US06996011B2
公开(公告)日：2006-02-07
申请号：US10855286
申请日：2004-05-26
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , H01L27/115
摘要： A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.
摘要翻译：由多个基本相同的EEPROM单元形成的NAND型可擦除可编程只读存储器（EEPROM）器件，每个EEPROM单元能够存储两位信息。用于操作存储器的简单方法包括擦除，编程和读取设备。

7. 发明授权

US07307888B2 Method and apparatus for operating nonvolatile memory in a parallel arrangement 有权
标题翻译：以并行方式操作非易失性存储器的方法和装置
公开(公告)号：US07307888B2
公开(公告)日：2007-12-11
申请号：US11191329
申请日：2005-07-28
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475
摘要： A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.
摘要翻译：具有电荷存储结构的存储单元通过测量存储单元的衬底区域和存储单元的一个载流节点之间的电流来读取。当电荷存储结构的其他部分存储不感兴趣的数据时，读取操作减小了电荷存储结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。示例性布置是单个存储器单元，列或NOR连接的存储器单元，以及存储器单元的虚拟接地阵列。

8. 发明授权

US07224619B2 Method and apparatus for protection from over-erasing nonvolatile memory cells 有权
标题翻译：用于防止过度擦除非易失性存储单元的方法和装置
公开(公告)号：US07224619B2
公开(公告)日：2007-05-29
申请号：US11223552
申请日：2005-09-09
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao-cheng Lu
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao-cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/3404
摘要： Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge in the erased state than in the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.
摘要翻译：电荷捕获存储器单元被保护以响应于擦除命令而被过擦除。例如，响应于擦除命令，将一个偏置装置应用于编程电荷俘获存储器单元，并且施加另一个偏置布置以擦除电荷捕获存储器单元，使得电荷捕获存储器单元具有较高的净电子电荷擦除状态比编程状态。在另一示例中，具有电荷俘获存储器单元阵列的集成电路具有通过向电荷捕获存储器单元施加相似的偏置布置来响应擦除命令的逻辑。在另一实例中，制造这种集成电路。

9. 发明授权

US07158411B2 Integrated code and data flash memory 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US07158411B2
公开(公告)日：2007-01-02
申请号：US10815370
申请日：2004-04-01
申请人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

10. 发明授权

US07486568B2 Method and apparatus for protection from over-erasing nonvolatile memory cells 有权
标题翻译：用于防止过度擦除非易失性存储单元的方法和装置
公开(公告)号：US07486568B2
公开(公告)日：2009-02-03
申请号：US11742398
申请日：2007-04-30
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/3404
摘要： Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge, in the erased state than i.n the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.
摘要翻译：电荷捕获存储器单元被保护以响应于擦除命令而被过擦除。例如，响应于擦除命令，将一个偏置装置应用于编程电荷俘获存储器单元，并且施加另一个偏置布置以擦除电荷捕获存储器单元，使得电荷捕获存储器单元具有较高的净电荷，处于擦除状态，而不是编程状态。在另一示例中，具有电荷俘获存储器单元阵列的集成电路具有通过向电荷捕获存储器单元施加相似的偏置布置来响应擦除命令的逻辑。在另一实例中，制造这种集成电路。

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