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1. 发明授权

US08501591B2 Method for manufacturing a multiple-bit-per-cell memory 有权
标题翻译：制造多位单元存储器的方法
公开(公告)号：US08501591B2
公开(公告)日：2013-08-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

2. 发明授权

US07132350B2 Method for manufacturing a programmable eraseless memory 有权
标题翻译：制造可编程擦除存储器的方法
公开(公告)号：US07132350B2
公开(公告)日：2006-11-07
申请号：US10641897
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

3. 发明授权

US07180123B2 Method for programming programmable eraseless memory 有权
标题翻译：编程可编程擦除存储器的方法
公开(公告)号：US07180123B2
公开(公告)日：2007-02-20
申请号：US10642249
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L29/76
CPC分类号： G11C11/5692 , G11C17/14 , G11C2211/5634 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.
摘要翻译：用于对存储单元进行编程的方法是基于向包括第一电极，第二电极和电极间层的存储单元施加应力，以引起电极间层的性能的逐渐变化。该方法包括验证步骤，包括生成指示所选择的存储单元中的属性的值的诸如单元电流的信号。然后，将信号与参考信号进行比较，以验证所需数据的编程。由于变革的渐进性，可以实现多层次的编程。多个编程级别可以应用于单个单元的编程，而不需要擦除处理，以编程单个单元中的多个位，以及多个位和多个编程时间的组合。

4. 发明授权

US06808995B2 Semiconductor device with minimal short-channel effects and low bit-line resistance 有权
标题翻译：半导体器件具有最小的短沟道效应和低位线电阻
公开(公告)号：US06808995B2
公开(公告)日：2004-10-26
申请号：US10361681
申请日：2003-02-11
申请人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
发明人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L29/78603 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/66757 , H01L29/66772
摘要： A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.
摘要翻译：一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物，以及形成在栅极氧化物上的栅极结构。

5. 发明授权

US06555844B1 Semiconductor device with minimal short-channel effects and low bit-line resistance 有权
标题翻译：半导体器件具有最小的短沟道效应和低位线电阻
公开(公告)号：US06555844B1
公开(公告)日：2003-04-29
申请号：US10101930
申请日：2002-03-21
申请人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
发明人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
IPC分类号： H01L31036
CPC分类号： H01L29/78603 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/66757 , H01L29/66772
摘要： A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.
摘要翻译：一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物，以及形成在栅极氧化物上的栅极结构。

6. 发明授权

US06498377B1 SONOS component having high dielectric property 有权
标题翻译：具有高介电性能的SONOS组件
公开(公告)号：US06498377B1
公开(公告)日：2002-12-24
申请号：US10101922
申请日：2002-03-21
申请人： Hung-Sui Lin , Nian Kai Zous , Han Chao Lai , Tao Cheng Lu
发明人： Hung-Sui Lin , Nian Kai Zous , Han Chao Lai , Tao Cheng Lu
IPC分类号： H01L29792
CPC分类号： H01L29/513 , H01L29/518 , H01L29/7923
摘要： A nitride read only memory device that includes a substrate having a source region, a drain region, and a channel region formed therebetween, a first oxide layer formed over the channel region, a nitride layer formed over the first oxide layer, a second oxide layer formed over the nitride layer, a gate structure formed over the second oxide layer, wherein a region in the substrate underneath the gate structure excludes one of the source and drain regions, a plurality of sidewall spacers formed over the nitride layer and contiguous with the gate structure, and at least one injection point for injecting electrons into the nitride layer, wherein the injection point is located at a junction between the channel region and one of the source and drain regions, and wherein electron charges are stored in portions of the nitride layer underneath the sidewall spacers.
摘要翻译：一种氮化物只读存储器件，其包括具有源极区，漏极区和在其间形成的沟道区的衬底，形成在沟道区上的第一氧化物层，形成在第一氧化物层上的氮化物层，第二氧化物层形成在所述氮化物层上方的栅极结构，形成在所述第二氧化物层上的栅极结构，其中所述栅极结构下方的所述衬底中的区域排除所述源极和漏极区之一;多个侧壁间隔物，形成在所述氮化物层上并与所述栅极连接结构，以及用于将电子注入到氮化物层中的至少一个注入点，其中注入点位于沟道区域和源区域和漏极区域之间的结处，并且其中电子电荷存储在氮化物层的部分中在侧壁间隔下面。

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