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1. 发明授权

US08501591B2 Method for manufacturing a multiple-bit-per-cell memory 有权
标题翻译：制造多位单元存储器的方法
公开(公告)号：US08501591B2
公开(公告)日：2013-08-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

2. 发明授权

US06671209B2 Erasing method for p-channel NROM 有权
标题翻译： p沟道NROM的擦除方法
公开(公告)号：US06671209B2
公开(公告)日：2003-12-30
申请号：US10035514
申请日：2001-10-22
申请人： Hung-Sui Lin , Han-Chao Lai , Tao-Cheng Lu
发明人： Hung-Sui Lin , Han-Chao Lai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/14
摘要： An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.
摘要翻译：用于p沟道氮化物只读存储器的擦除方法。该方法用于具有存储在电荷捕获层中的电荷的p沟道氮化物只读存储器。向控制栅极施加正电压，向漏极施加负电压; 源也是浮动的，n阱是接地的。施加到控制栅极的正电压和到漏极的负电压之间的电压差足以触发带间感应的热电子注入以擦除p沟道氮化物只读存储器。

3. 发明授权

US06492235B2 Method for forming extension by using double etch spacer 有权
标题翻译：通过使用双蚀刻间隔物形成延伸的方法
公开(公告)号：US06492235B2
公开(公告)日：2002-12-10
申请号：US09770550
申请日：2001-01-26
申请人： Han-Chao Lai , Tao-Cheng Lu , Hung-Sui Lin
发明人： Han-Chao Lai , Tao-Cheng Lu , Hung-Sui Lin
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/665 , H01L29/6653
摘要： A method for forming extension by using double etch spacer. The method includes at least the following steps. First a semiconductor substrate is provided. Then, the gate is formed on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted in the substrate by a mask of both the gate and the first spacer to form the source/drain region. Then, the second spacer is formed by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted in the substrate by a mask of both the gate and the second spacer to form an extension.
摘要翻译：通过使用双蚀刻间隔物形成延伸的方法。该方法至少包括以下步骤。首先提供半导体衬底。然后，在基板上形成栅极。第一间隔件形成在栅极的侧壁上。然后，通过栅极和第一间隔物的掩模将许多第一离子注入到衬底中以形成源极/漏极区。然后，通过蚀刻第一间隔物形成第二间隔物，其中第二间隔物的宽度小于第一间隔物的宽度。最后，通过栅极和第二间隔物的掩模将许多第二离子注入到衬底中以形成延伸。

4. 发明授权

US06458643B1 Method of fabricating a MOS device with an ultra-shallow junction 有权
标题翻译：制造具有超浅结的MOS器件的方法
公开(公告)号：US06458643B1
公开(公告)日：2002-10-01
申请号：US09681984
申请日：2001-07-03
申请人： Han-Chao Lai , Tao-Cheng Lu , Hung-Sui Lin
发明人： Han-Chao Lai , Tao-Cheng Lu , Hung-Sui Lin
IPC分类号： H01L218238
CPC分类号： H01L29/7833 , H01L21/2652 , H01L21/324 , H01L29/66492 , H01L29/6659
摘要： A semiconductor substrate is provided with at least a gate formed on the semiconductor substrate. A first ion implantation process is performed to form a pocket implant region within the semiconductor substrate beneath the gate. Following the first ion implantation process, a first rapid thermal annealing (RTA) process is immediately performed to reduce TED effects resulting from the first ion implantation process. Thereafter, a second implantation process is performed to form a source extension doping region and a drain extension doping region within the semiconductor substrate adjacent to the gate. A source doping region and a drain doping region are then formed within the semiconductor substrate adjacent to the gate. Finally, a second RTA process is performed to simultaneously activate dopants in the source extension doping region, the drain extension doping region, the source doping region and the drain doping region.
摘要翻译：半导体衬底至少设置有形成在半导体衬底上的栅极。执行第一离子注入工艺以在栅极下方的半导体衬底内形成凹穴注入区域。在第一离子注入工艺之后，立即执行第一快速热退火（RTA）工艺以降低由第一离子注入工艺产生的TED效应。此后，执行第二注入工艺以在与栅极相邻的半导体衬底内形成源极延伸掺杂区域和漏极延伸掺杂区域。然后在与栅极相邻的半导体衬底内形成源极掺杂区域和漏极掺杂区域。最后，执行第二RTA工艺以同时激活源延伸掺杂区域，漏极延伸掺杂区域，源极掺杂区域和漏极掺杂区域中的掺杂剂。

5. 发明授权

US06620693B2 Non-volatile memory and fabrication thereof 有权
标题翻译：非易失性存储器及其制造
公开(公告)号：US06620693B2
公开(公告)日：2003-09-16
申请号：US10055491
申请日：2002-01-22
申请人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
发明人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
IPC分类号： H01L218234
CPC分类号： H01L27/11213 , H01L27/105 , H01L27/1126 , H01L27/11293
摘要： A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step; The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.
摘要翻译：描述了制造非易失性存储器的方法。首先在衬底中形成平面掺杂区域。在衬底上依次形成掩模层和图案化的光致抗蚀剂层。在衬底中形成多个沟槽，其中图案化的光致抗蚀剂层作为掩模将平面掺杂区域分成多个位线。去除图案化的光致抗蚀剂层，然后执行恢复过程以从沟槽蚀刻步骤引起的损伤中回收沟槽的侧壁和底部; 去除掩模层。在基板上形成电介质层，然后在电介质层上形成多个字线。

6. 发明授权

US06635946B2 Semiconductor device with trench isolation structure 有权
公开(公告)号：US06635946B2
公开(公告)日：2003-10-21
申请号：US09930304
申请日：2001-08-16
申请人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
发明人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
IPC分类号： H01L2976
CPC分类号： H01L29/0649 , H01L21/7624 , H01L29/66651 , H01L29/78654
摘要： A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.

7. 发明授权

US06524919B2 Method for manufacturing a metal oxide semiconductor with a sharp corner spacer 有权
标题翻译：具有尖锐角隔离物的金属氧化物半导体的制造方法
公开(公告)号：US06524919B2
公开(公告)日：2003-02-25
申请号：US09950215
申请日：2001-09-07
申请人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
发明人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a metal oxide semiconductor device is provided comprising the steps of: performing an ion implantation to form a source/drain region in the substrate having a gate formed on it and a spacer formed on the sidewalls of the gate; forming a self-aligned silicide layer on the exposed surface of the gate and the source/drain region; removing a portion of the spacer to form a substantially triangular spacer with sharp corners; performing a tilted pocket implantation to form pocket regions within the substrate beside the gate, and controlling the location of the pocket regions and the dopant distribution by adjusting the energy and angle of the tilted pocket implantation; performing a tilted-angle implantation to form a source/drain extension within the substrate beside the gate and underlying the spacer; using the thermal cycle process to adjust the junction depth and the doping profile of the source/drain extension.
摘要翻译：提供一种制造金属氧化物半导体器件的方法，包括以下步骤：进行离子注入以在其上形成有栅极的基板和形成在栅极的侧壁上的间隔物形成源极/漏极区域; 在栅极和源极/漏极区域的暴露表面上形成自对准的硅化物层; 去除间隔物的一部分以形成具有尖角的基本上三角形的间隔物; 执行倾斜的袋注入以在栅极旁边的衬底内形成袋区，并且通过调整倾斜袋植入的能量和角度来控制袋区的位置和掺杂剂分布; 执行倾斜角度注入以在栅极旁边的衬底内以及衬垫下方形成源极/漏极延伸部; 使用热循环过程来调节源极/漏极延伸的结深度和掺杂分布。

8. 发明授权

US06448142B1 Method for fabricating a metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US06448142B1
公开(公告)日：2002-09-10
申请号：US09922255
申请日：2001-08-03
申请人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
发明人： Han-Chao Lai , Hung-Sui Lin , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/2652 , H01L21/26586 , H01L29/665 , H01L29/6653
摘要： A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.
摘要翻译：对金属氧化物半导体晶体管的制造方法进行说明。源极/漏极注入在位于栅极的侧壁上的间隔物旁边的衬底上进行，以在隔板旁边的衬底中形成源极/漏极区域。在栅极和源极/漏极区域上进一步形成自对准的硅化物层。去除间隔物的一部分以形成具有锐角的三角形间隔物，随后在衬底上进行倾斜角度注入，以在栅极侧面的衬底中形成源极/漏极延伸区域，并且具有尖锐的衬垫角。进一步进行热循环以调节源极/漏极延伸区域的结深度和掺杂物分布。

9. 发明授权

US06808995B2 Semiconductor device with minimal short-channel effects and low bit-line resistance 有权
标题翻译：半导体器件具有最小的短沟道效应和低位线电阻
公开(公告)号：US06808995B2
公开(公告)日：2004-10-26
申请号：US10361681
申请日：2003-02-11
申请人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
发明人： Hung-Sui Lin , Han Chao Lai , Tao Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L29/78603 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/66757 , H01L29/66772
摘要： A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.
摘要翻译：一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物，以及形成在栅极氧化物上的栅极结构。

10. 发明授权

US06720614B2 Operation method for programming and erasing a data in a P-channel sonos memory cell 有权
标题翻译：用于编程和擦除P信道声纳存储单元中的数据的操作方法
公开(公告)号：US06720614B2
公开(公告)日：2004-04-13
申请号：US10005270
申请日：2001-12-04
申请人： Hung-Sui Lin , Nian-Kai Zous , Han-Chao Lai , Tao-Cheng Lu
发明人： Hung-Sui Lin , Nian-Kai Zous , Han-Chao Lai , Tao-Cheng Lu
IPC分类号： H01L29788
CPC分类号： G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.
摘要翻译：一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。两个掺杂区域被设置为漏极区域和源极区域。当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。第三负电压大于绝对值中的第二负偏压。

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