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1. 发明授权

US12080344B2 Radiation hardened e-fuse macro 有权
公开(公告)号：US12080344B2
公开(公告)日：2024-09-03
申请号：US17552844
申请日：2021-12-16
申请人： BAE SYSTEMS Information and Electronic Systems Integration Inc.
发明人： Jason F. Ross
IPC分类号： G11C11/56 , G11C17/16 , G11C17/18
CPC分类号： G11C11/5692 , G11C17/16 , G11C17/18
摘要： A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with said e-fuse macro.

2. 发明申请

US20170278582A1 Read-Only Memory (ROM) Architecture with Selective Encoding 有权
公开(公告)号：US20170278582A1
公开(公告)日：2017-09-28
申请号：US15143160
申请日：2016-04-29
申请人： Broadcom Corporation
发明人： Dechang SUN , Wei ZHANG , Mai T. MAC LENNAN , Sudeep Ashok POMAR , Roy M. CARLSON
IPC分类号： G11C17/08
CPC分类号： G11C17/14 , G11C7/067 , G11C7/12 , G11C7/18 , G11C11/5692 , G11C14/00 , G11C17/08 , G11C17/10
摘要： Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

3. 发明授权

US09502132B2 Multi level antifuse memory device and method of operating the same 有权
标题翻译：多级反熔丝存储装置及其操作方法
公开(公告)号：US09502132B2
公开(公告)日：2016-11-22
申请号：US13912649
申请日：2013-06-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Min-Soo Jang , Young-hun Seo , Chan-yong Lee
IPC分类号： G11C7/06 , G11C17/16 , G11C17/18 , G11C11/56
CPC分类号： G11C17/16 , G11C11/5692 , G11C17/18 , G11C2211/5624 , G11C2211/563
摘要： An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.
摘要翻译：反熔丝存储器件包括反熔丝存储单元，参考电流产生单元和比较单元。反熔丝存储单元包括反熔丝。参考电流产生单元提供从多个参考电流中选择的参考电流。比较单元将流过反熔丝的单元电流的强度与参考电流的强度进行比较，并提供与比较结果相对应的输出信号。

4. 发明授权

US09502102B1 MLC OTP operation with diode behavior in ZnO RRAM devices for 3D memory 有权
标题翻译：用于3D存储器的ZnO RRAM器件中具有二极管特性的MLC OTP操作
公开(公告)号：US09502102B1
公开(公告)日：2016-11-22
申请号：US14341726
申请日：2014-07-25
申请人： Crossbar, Inc.
发明人： Tanmay Kumar , Sung Hyun Jo
IPC分类号： G11C13/02 , G11C11/56 , H01L45/00 , G11C13/00
CPC分类号： G11C11/5692 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C17/165 , G11C17/18 , G11C2013/0083 , G11C2213/15 , G11C2213/52 , G11C2213/73 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is described herein. In some embodiments, one time programmable, multi-level cell two-terminal memory cell can exhibit diode-like characteristics. In other embodiments, the memory cell can comprise a first electrode layer configured to generate ions in response to an electric field applied to the memory cell; a resistive ion migration layer at least in part permeable to migration of the ions within the resistive ion migration layer; a second electrode layer; and a substrate layer comprising a silicon wafer.
摘要翻译：提供能够形成一次可编程的多电平单元两端存储器单元或可重写的两端存储单元的存储单元。在一些实施例中，一次可编程的多电平单元两端存储器单元可以表现出二极管状特性。在其他实施例中，存储器单元可以包括配置成响应于施加到存储器单元的电场而产生离子的第一电极层; 电阻离子迁移层至少部分可透过电离离子迁移层内的离子迁移; 第二电极层; 以及包括硅晶片的基底层。

5. 发明授权

US09336894B2 Memory device including nonvolatile memory cell 有权
标题翻译：存储器件包括非易失性存储单元
公开(公告)号：US09336894B2
公开(公告)日：2016-05-10
申请号：US14753620
申请日：2015-06-29
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Min Choi , Shigenobu Maeda , Ji-Hoon Yoon
IPC分类号： G11C17/00 , G11C17/08 , G11C13/00
CPC分类号： G11C13/004 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/0069 , G11C17/165 , G11C17/18 , G11C2213/53
摘要： A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
摘要翻译：存储器件可以包括非易失性存储器单元。非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值大于第四电阻值且大于第四电阻值。

6. 发明申请

US20160092284A1 ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS 有权
标题翻译：使用选择性错误来评估闪光质量
公开(公告)号：US20160092284A1
公开(公告)日：2016-03-31
申请号：US14501081
申请日：2014-09-30
申请人： APPLE INC.
发明人： Yael Shur , Eyal Gurgi , Moshe Neerman , Naftali Sommer
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , G06F11/073 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C11/5692 , G11C16/26 , G11C29/00 , G11C29/42
摘要： A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.
摘要翻译：一种用于数据存储的方法包括：从存储器件读取作为相应模拟值存储在一组存储器单元中的数据，并将读出的数据中的读出错误分类为至少第一和第二不同类型，这取决于模拟价值下降。基于第一和第二类型的读出错误的评估数，将强调第二类型的读出错误的存储器质量分配给存储器单元组。

7. 发明授权

US09251893B2 Multiple-bit programmable resistive memory using diode as program selector 有权
标题翻译：使用二极管作为程序选择器的多位可编程电阻存储器
公开(公告)号：US09251893B2
公开(公告)日：2016-02-02
申请号：US13590044
申请日：2012-08-20
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C11/00 , G11C11/56 , G11C13/00
CPC分类号： G11C11/5678 , G11C11/5685 , G11C11/5692 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/0092 , G11C2213/72 , G11C2213/74
摘要： A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2n (n>1) distinct resistance levels to store n-bit data, at least 2n−1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.
摘要翻译：公开了一种具有多位可编程电阻元件并使用二极管作为程序选择器的多位可编程电阻单元的方法和系统。具有第一和第二类掺杂剂的二极管的第一和第二端可以由用于MOS器件的阱中的MOS的源极/漏极制造或者制造在相同的多晶硅结构上。如果多位可编程电阻单元具有2n（n> 1）个不同的电阻电平来存储n位数据，则可以将至少2n-1个参考电阻电平指定为两个相邻状态之间的差分电阻。编程多位可编程电阻元件可以通过应用具有初始编程电压（或电流）和持续时间的编程脉冲来启动。可以遵循读取验证周期来确定是否达到所需的电阻值。如果尚未达到所需的电阻值，则可以应用附加的编程脉冲。

8. 发明授权

US09159413B2 Thermo programmable resistor based ROM 有权
标题翻译：基于可编程电阻的ROM
公开(公告)号：US09159413B2
公开(公告)日：2015-10-13
申请号：US12981379
申请日：2010-12-29
申请人： Olivier Le Neel , Jean Jimenez
发明人： Olivier Le Neel , Jean Jimenez
IPC分类号： G11C13/00 , G11C11/56 , G11C17/18 , H01L27/10 , H01L27/105 , H01L49/02 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/18 , G11C2013/008 , G11C2213/33 , H01L27/101 , H01L27/1052 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L28/20 , H01L45/04 , H01L45/1226 , H01L45/1286 , H01L45/14 , H01L45/148
摘要： An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.
摘要翻译：形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。每个存储单元具有可调电阻器和加热元件。电介质材料将加热元件与可调电阻器分开。加热元件通过向其施加热量来改变电阻器的电阻。可调电阻器的电阻的大小表示存储在存储单元中的数据的值。

9. 发明授权

US09147495B2 Two-bit read-only memory cell 有权
标题翻译：两位只读存储单元
公开(公告)号：US09147495B2
公开(公告)日：2015-09-29
申请号：US13778258
申请日：2013-02-27
申请人： LSI Corporation
发明人： Rajiv Kumar Roy , Vikash
IPC分类号： G11C11/4097 , G11C17/14 , G11C11/56
CPC分类号： G11C17/146 , G11C11/4097 , G11C11/5692
摘要： A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
摘要翻译：只读存储器（ROM）单元具有串联在真位线和电压基准（例如，接地）之间的第一和第二晶体管，以及串联连接在补码位线和电压基准之间的第三和第四晶体管。第一和第三晶体管的栅极连接到第一字线，第二和第四晶体管的栅极连接到第二字线。 ROM单元被编程为通过适当地（i）将第一和第二晶体管之间的节点连接到真位线，补码位线或电压基准来存储两位信息的任何可能的组合，以及（ii）连接第三和第四晶体管之间的节点到真位线，补码位线或电压基准。

10. 发明申请

US20140219016A1 SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL 有权
标题翻译：编程存储器单元的系统和方法
公开(公告)号：US20140219016A1
公开(公告)日：2014-08-07
申请号：US13759344
申请日：2013-02-05
申请人： QUALCOMM INCORPORATED
发明人： Xia Li , Bin Yang
IPC分类号： G11C7/12 , G11C11/40 , G06F17/50
CPC分类号： G11C17/18 , G06F17/5045 , G11C5/06 , G11C5/146 , G11C7/12 , G11C11/40 , G11C11/404 , G11C11/5692 , G11C16/04 , G11C17/16 , G11C2211/4016
摘要： A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.
摘要翻译：一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

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