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1. 发明授权

US06998663B2 Semiconductor device having capacitor and method of manufacturing the same 失效
公开(公告)号：US06998663B2
公开(公告)日：2006-02-14
申请号：US10770489
申请日：2004-02-04
申请人： Takashi Yoshitomi , Masahiko Matsumoto
发明人： Takashi Yoshitomi , Masahiko Matsumoto
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/40
摘要： A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.

2. 发明授权

US06746929B2 Semiconductor device having capacitor and method of manufacturing the same 失效
公开(公告)号：US06746929B2
公开(公告)日：2004-06-08
申请号：US10263186
申请日：2002-10-03
申请人： Takashi Yoshitomi , Masahiko Matsumoto
发明人： Takashi Yoshitomi , Masahiko Matsumoto
IPC分类号： H01L2120
CPC分类号： H01L28/40
摘要： A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.

3. 发明授权

US06983402B2 Computer device 失效
公开(公告)号：US06983402B2
公开(公告)日：2006-01-03
申请号：US10006134
申请日：2001-12-10
申请人： Takashi Yoneda , Masahiko Matsumoto
发明人： Takashi Yoneda , Masahiko Matsumoto
IPC分类号： G06F11/00
CPC分类号： G06F11/1497 , G06F9/3802 , G06F9/3861
摘要： In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.

4. 发明授权

US5966514A Microprocessor for supporting reduction of program codes in size 失效
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US5966514A
公开(公告)日：1999-10-12
申请号：US643947
申请日：1996-05-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

5. 发明授权

US4355038A .alpha.-Substituted ureido-benzylpenicillanic acids 失效
标题翻译： α-取代的脲基 - 苄基青霉烷酸
公开(公告)号：US4355038A
公开(公告)日：1982-10-19
申请号：US288402
申请日：1981-07-30
申请人： Nobuhiro Oi , Bunya Aoki , Teizo Shinozaki , Kanji Moro , Toshio Kuroki , Isao Matsunaga , Takao Noto , Toshiyuki Nebashi , Yusuke Harada , Hisao Endo , Takao Kimura , Kana Kojima , Masahiko Matsumoto , Hiroshi Okazaki , Haruki Ogawa , Minoru Shindo
发明人： Nobuhiro Oi , Bunya Aoki , Teizo Shinozaki , Kanji Moro , Toshio Kuroki , Isao Matsunaga , Takao Noto , Toshiyuki Nebashi , Yusuke Harada , Hisao Endo , Takao Kimura , Kana Kojima , Masahiko Matsumoto , Hiroshi Okazaki , Haruki Ogawa , Minoru Shindo
IPC分类号： C07D499/68 , A61K31/43 , A61P31/04 , C07D499/00 , C07D499/64
CPC分类号： C07D499/00 , Y02P20/55
摘要： .alpha.-Substituted ureido-benzylpenicillanic acids of the formula ##STR1## (wherein R.sup.1, X and Y are as defined in the description) and pharmaceutically acceptable salts thereof, and a bactericidal composition comprising the above penicillanic acid or the salt and a pharmaceutically acceptable carrier are disclosed. The acids and salts thereof have high antibacterial activities against Gram-positive and Gram-negative bacteria, particularly those of the genus Pseudomonas.
摘要翻译：式（IMA）（其中R1，X和Y如说明书中所定义）的α-取代的脲基 - 苄基青霉烷酸及其药学上可接受的盐，以及包含上述青霉烷酸或其药学上可接受的载体的杀菌组合物被披露。其酸和盐对革兰氏阳性和革兰氏阴性细菌，特别是假单胞菌属的抗菌活性具有很高的抗菌活性。

6. 发明授权

US06682967B2 Semiconductor device and method of making the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06682967B2
公开(公告)日：2004-01-27
申请号：US10127507
申请日：2002-04-23
申请人： Masahiko Matsumoto , Hirofumi Igarashi
发明人： Masahiko Matsumoto , Hirofumi Igarashi
IPC分类号： H01L218238
CPC分类号： H01L21/76235 , Y10S438/942
摘要： A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.
摘要翻译：半导体器件包括半导体衬底，在半导体衬底中形成的p型阱，在半导体衬底中形成并且邻近p型阱定位的n型阱，形成在p型阱中的n型扩散区，以及形成在n型阱中的p型扩散区域，其中在p型阱和n型阱之间的边界图案的一部分中存在内侧具有p型阱的角C1，类型很好。限定拐角C1的两侧中的至少一个从预定长度的预定宽度d从角部的顶部延伸到n孔。该特定结构允许抑制半导体器件的阱边界的角部和直线部分之间的隔离穿透电压的差异的产生，使得可以提供精细的器件结构，同时确保期望的隔离穿孔 - 通过电压不放松设计规则。

7. 发明授权

US06525402B1 Semiconductor wafer, method of manufacturing the same and semiconductor device 失效
标题翻译：半导体晶片及其制造方法以及半导体器件
公开(公告)号：US06525402B1
公开(公告)日：2003-02-25
申请号：US09395204
申请日：1999-09-14
申请人： Masahiko Matsumoto , Hisato Oyamatsu , Takeo Nakayama , Yasuhiro Fukaura , Kunihiro Kasai , Masahiro Inohara
发明人： Masahiko Matsumoto , Hisato Oyamatsu , Takeo Nakayama , Yasuhiro Fukaura , Kunihiro Kasai , Masahiro Inohara
IPC分类号： H01L2358
CPC分类号： H01L21/32051
摘要： The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.
摘要翻译：本发明的目的是提供一种半导体晶片，其中防止通过诸如Cu布线形成步骤的热处理产生的Cu的扩散进入硅，并减小晶体管特性的变化。本发明的目的是提供一种制造该半导体器件的方法和由该半导体器件制成的半导体器件。在本发明中，在周边部分形成有用于防止Cu扩散到晶片内部的保护绝缘膜的主平面，外侧面和后平面。利用该保护绝缘膜，防止了作为布线材料的Cu扩散到晶片的芯片形成区域，使得晶体管特性的变化。

8. 发明授权

US06399992B1 Semiconductor device and method of making the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06399992B1
公开(公告)日：2002-06-04
申请号：US09819619
申请日：2001-03-29
申请人： Masahiko Matsumoto , Hirofumi Igarashi
发明人： Masahiko Matsumoto , Hirofumi Igarashi
IPC分类号： H01L31119
CPC分类号： H01L21/76235 , Y10S438/942
摘要： A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.
摘要翻译：半导体器件包括半导体衬底，在半导体衬底中形成的p型阱，在半导体衬底中形成并且邻近p型阱定位的n型阱，形成在p型阱中的n型扩散区，以及形成在n型阱中的p型扩散区域，其中在p型阱和n型阱之间的边界图案的一部分中存在内侧具有p型阱的角C1，类型很好。限定拐角C1的两侧中的至少一个从预定长度的预定宽度d从角部的顶部延伸到n孔。该特定结构允许抑制半导体器件的阱边界的角部和直线部分之间的隔离穿透电压的差异的产生，使得可以提供精细的器件结构，同时确保期望的隔离穿孔 - 通过电压不放松设计规则。

9. 发明授权

US06253305B1 Microprocessor for supporting reduction of program codes in size 有权
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US06253305B1
公开(公告)日：2001-06-26
申请号：US09226791
申请日：1999-01-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

10. 发明授权

US4807574A Valve operating device for internal combustion engine 失效
公开(公告)号：US4807574A
公开(公告)日：1989-02-28
申请号：US137954
申请日：1987-12-24
申请人： Mitsuhiro Shibata , Kazuhide Kumagai , Koichi Fukuo , Toshiaki Hiro , Masahiko Matsumoto
发明人： Mitsuhiro Shibata , Kazuhide Kumagai , Koichi Fukuo , Toshiaki Hiro , Masahiko Matsumoto
IPC分类号： F01L1/26 , F01M1/16 , F01M9/10 , F02F1/24 , F02F1/42 , F01L1/18
CPC分类号： F01M1/16 , F01L1/26 , F01L1/267 , F01M9/101 , F02F1/4214 , F02F2001/247
摘要： A valve operating mechanism for an internal combustion engine has a low-speed cam for operating the intake or exhaust valves during low-speed operation of the engine and a high-speed cam for operating the intake or exhaust valves during high-speed operation of the engine. A low-speed lubricating oil passage is provided for supplying lubricating oil to the low-speed cam and a separate high-speed lubricating oil passage is provided for supplying lubricating oil to the high-speed cam. A control valve is connected to said low-speed and high-speed lubricating oil passages for selectively supplying maximum oil pressure to the high-speed lubricating oil passage during high-speed operation while restricting the rate of flow of oil during low-speed operation of the engine and supplying maximum oil pressure to the low-speed lubricating oil passage during low-speed operation of the engine while restricting or eliminating the oil supplied thereto during high-speed operation.

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