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    • 6. 发明授权
    • Semiconductor device and method of making the same
    • 半导体器件及其制造方法
    • US06682967B2
    • 2004-01-27
    • US10127507
    • 2002-04-23
    • Masahiko MatsumotoHirofumi Igarashi
    • Masahiko MatsumotoHirofumi Igarashi
    • H01L218238
    • H01L21/76235Y10S438/942
    • A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.
    • 半导体器件包括半导体衬底,在半导体衬底中形成的p型阱,在半导体衬底中形成并且邻近p型阱定位的n型阱,形成在p型阱中的n型扩散区, 以及形成在n型阱中的p型扩散区域,其中在p型阱和n型阱之间的边界图案的一部分中存在内侧具有p型阱的角C1, 类型很好。 限定拐角C1的两侧中的至少一个从预定长度的预定宽度d从角部的顶部延伸到n孔。 该特定结构允许抑制半导体器件的阱边界的角部和直线部分之间的隔离穿透电压的差异的产生,使得可以提供精细的器件结构,同时确保期望的隔离穿孔 - 通过电压不放松设计规则。
    • 8. 发明授权
    • Semiconductor device and method of making the same
    • 半导体器件及其制造方法
    • US06399992B1
    • 2002-06-04
    • US09819619
    • 2001-03-29
    • Masahiko MatsumotoHirofumi Igarashi
    • Masahiko MatsumotoHirofumi Igarashi
    • H01L31119
    • H01L21/76235Y10S438/942
    • A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.
    • 半导体器件包括半导体衬底,在半导体衬底中形成的p型阱,在半导体衬底中形成并且邻近p型阱定位的n型阱,形成在p型阱中的n型扩散区, 以及形成在n型阱中的p型扩散区域,其中在p型阱和n型阱之间的边界图案的一部分中存在内侧具有p型阱的角C1, 类型很好。 限定拐角C1的两侧中的至少一个从预定长度的预定宽度d从角部的顶部延伸到n孔。 该特定结构允许抑制半导体器件的阱边界的角部和直线部分之间的隔离穿透电压的差异的产生,使得可以提供精细的器件结构,同时确保期望的隔离穿孔 - 通过电压不放松设计规则。