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    • 4. 发明授权
    • Semiconductor device with an improved gate electrode pattern
    • 具有改善的栅极电极图案的半导体器件
    • US06653695B2
    • 2003-11-25
    • US09418035
    • 1999-10-14
    • Hisato Oyamatsu
    • Hisato Oyamatsu
    • H01L2976
    • H01L27/11H01L27/1104H01L29/4238Y10S257/903Y10S257/904
    • Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.
    • 公开了使用诸如SRAM的栅电极的半导体器件,其中电极图案通过没有复杂的布局设计形成为与保护膜图案保持一致。 栅电极图案形成在比常规半导体器件小的区域中。 在使用设置有基本上线性的栅电极图案的掩模图案的光刻步骤中,形成有布置有至少一部分接触区域的突出部分,使得其包括在线性栅极的长边的几乎中心 电极图案和至少面向突出部分的整个长度的凹部形成为使得它被包括在与标线图案的晶体管区域之间的突出部分相对的长边中。
    • 5. 发明授权
    • Semiconductor device having structure suitable for CMP process
    • 半导体器件具有适用于CMP工艺的结构
    • US6091130A
    • 2000-07-18
    • US996402
    • 1997-12-22
    • Hisato OyamatsuMasayuki Murota
    • Hisato OyamatsuMasayuki Murota
    • H01L21/304H01L21/02H01L21/3105H01L29/06H01L21/302H01L21/461
    • H01L29/0657H01L21/31053
    • A convex portion is formed along the edge of a semiconductor substrate to surround a chip region on the main surface side of the semiconductor substrate. For example, the convex portion is formed part of the semiconductor substrate. The height of the convex portion is set to approximately the same height as the surface of an insulating film attained after the end of the CMP (chemical mechanical polishing) process effected for the insulating film. The width the of the convex portion is set smaller than the width from the edge of the semiconductor substrate to a position in front of the chip region. The semiconductor substrate is attached to a carrier and the CMP process is effected by use of a polishing pad and a slurry. At the time of CMP, since a local heavy load occurring in the edge portion of the semiconductor substrate is applied only to the convex portion, the wafer edge over-polishing will not occur.
    • 沿着半导体衬底的边缘形成凸部,以围绕半导体衬底的主表面侧的芯片区域。 例如,凸部形成半导体基板的一部分。 凸部的高度设定为在对绝缘膜进行CMP(化学机械抛光)处理结束后达到的绝缘膜的表面大致相同的高度。 凸部的宽度被设定为小于从半导体衬底的边缘到芯片区域前方的位置的宽度。 半导体衬底附接到载体上,并且CMP工艺通过使用抛光垫和浆料来实现。 在CMP时,由于仅在半导体基板的边缘部分产生的局部重负荷仅施加到凸部,所以不会发生晶片边缘抛光。