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1. 发明申请

US20060273330A1 Semiconductor device using partial SOI substrate and manufacturing method thereof 失效
标题翻译：使用部分SOI衬底的半导体器件及其制造方法
公开(公告)号：US20060273330A1
公开(公告)日：2006-12-07
申请号：US11498774
申请日：2006-08-04
申请人： Hajime Nagano , Shinichi Nitta , Hisato Oyamatsu
发明人： Hajime Nagano , Shinichi Nitta , Hisato Oyamatsu
IPC分类号： H01L33/00
CPC分类号： H01L27/10894 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L21/76278 , H01L21/76283 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.
摘要翻译：一种半导体器件制造方法，包括：选择性地去除SOI衬底中的一部分掩埋氧化物层和第一半导体层，所述SOI衬底具有形成于半导体衬底上方的所述掩埋氧化物层的第一半导体层，并且暴露所述半导体衬底的一部分，区域，并且在半导体衬底的一部分已经在深度方向上被去除的区域中埋入第二半导体区域。

2. 发明授权

US06906384B2 Semiconductor device having one of patterned SOI and SON structure 失效
标题翻译：具有图案化SOI和SON结构之一的半导体器件
公开(公告)号：US06906384B2
公开(公告)日：2005-06-14
申请号：US10096655
申请日：2002-03-14
申请人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
发明人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/10861 , H01L21/76243 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/78639
摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.
摘要翻译：半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。第一半导体层设置在半导体衬底上并与之电连接。第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

3. 发明授权

US06724046B2 Semiconductor device having patterned SOI structure and method for fabricating the same 有权
公开(公告)号：US06724046B2
公开(公告)日：2004-04-20
申请号：US10075465
申请日：2002-02-15
申请人： Hisato Oyamatsu
发明人： Hisato Oyamatsu
IPC分类号： H01L2701
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10861 , H01L27/1203
摘要： A semiconductor device includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is formed in a first region of the semiconductor substrate. The second semiconductor layer is formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer. The third semiconductor layer is formed in a third region of a part of the semiconductor substrate with the insulation film and the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer. The top surface of the third semiconductor layer is higher than that of the second semiconductor layer in the second region.

4. 发明授权

US06653695B2 Semiconductor device with an improved gate electrode pattern 失效
标题翻译：具有改善的栅极电极图案的半导体器件
公开(公告)号：US06653695B2
公开(公告)日：2003-11-25
申请号：US09418035
申请日：1999-10-14
申请人： Hisato Oyamatsu
发明人： Hisato Oyamatsu
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104 , H01L29/4238 , Y10S257/903 , Y10S257/904
摘要： Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.
摘要翻译：公开了使用诸如SRAM的栅电极的半导体器件，其中电极图案通过没有复杂的布局设计形成为与保护膜图案保持一致。栅电极图案形成在比常规半导体器件小的区域中。在使用设置有基本上线性的栅电极图案的掩模图案的光刻步骤中，形成有布置有至少一部分接触区域的突出部分，使得其包括在线性栅极的长边的几乎中心电极图案和至少面向突出部分的整个长度的凹部形成为使得它被包括在与标线图案的晶体管区域之间的突出部分相对的长边中。

5. 发明授权

US6091130A Semiconductor device having structure suitable for CMP process 失效
标题翻译：半导体器件具有适用于CMP工艺的结构
公开(公告)号：US6091130A
公开(公告)日：2000-07-18
申请号：US996402
申请日：1997-12-22
申请人： Hisato Oyamatsu , Masayuki Murota
发明人： Hisato Oyamatsu , Masayuki Murota
IPC分类号： H01L21/304 , H01L21/02 , H01L21/3105 , H01L29/06 , H01L21/302 , H01L21/461
CPC分类号： H01L29/0657 , H01L21/31053
摘要： A convex portion is formed along the edge of a semiconductor substrate to surround a chip region on the main surface side of the semiconductor substrate. For example, the convex portion is formed part of the semiconductor substrate. The height of the convex portion is set to approximately the same height as the surface of an insulating film attained after the end of the CMP (chemical mechanical polishing) process effected for the insulating film. The width the of the convex portion is set smaller than the width from the edge of the semiconductor substrate to a position in front of the chip region. The semiconductor substrate is attached to a carrier and the CMP process is effected by use of a polishing pad and a slurry. At the time of CMP, since a local heavy load occurring in the edge portion of the semiconductor substrate is applied only to the convex portion, the wafer edge over-polishing will not occur.
摘要翻译：沿着半导体衬底的边缘形成凸部，以围绕半导体衬底的主表面侧的芯片区域。例如，凸部形成半导体基板的一部分。凸部的高度设定为在对绝缘膜进行CMP（化学机械抛光）处理结束后达到的绝缘膜的表面大致相同的高度。凸部的宽度被设定为小于从半导体衬底的边缘到芯片区域前方的位置的宽度。半导体衬底附接到载体上，并且CMP工艺通过使用抛光垫和浆料来实现。在CMP时，由于仅在半导体基板的边缘部分产生的局部重负荷仅施加到凸部，所以不会发生晶片边缘抛光。

6. 发明授权

US5691564A Semiconductor device with high speed operation and high integration 失效
标题翻译：半导体器件具有高速运行和高集成度
公开(公告)号：US5691564A
公开(公告)日：1997-11-25
申请号：US566490
申请日：1995-12-04
申请人： Hisato Oyamatsu
发明人： Hisato Oyamatsu
IPC分类号： H01L21/265 , H01L21/76 , H01L21/762 , H01L29/10 , H01L29/00 , H01L27/108 , H01L29/76
CPC分类号： H01L21/76218 , H01L29/1083
摘要： A semiconductor device manufactured by isolating an element by forming an insulating film on the surface of a semiconductor substrate at an element isolation region, selectively forming a resist film at a second region on the surface of the semiconductor substrate by photolithography, high speed operation having priority over high integration in the second region, and selectively implanting impurity ions as a channel stopper in a first region by using the resist film as a mask, high integration having priority over high speed operation in the first region.
摘要翻译：一种半导体器件，其通过在元件隔离区域的半导体衬底的表面上形成绝缘膜来隔离元件而制造，通过光刻在半导体衬底的表面上的第二区域选择性地形成抗蚀剂膜，具有优先的高速操作通过使用抗蚀剂膜作为掩模在第一区域中选择性地将杂质离子作为通道阻挡物注入第二区域中，在第一区域中具有优先于高速操作的高集成度。

7. 发明授权

US07741159B2 Semiconductor device having channel with cooling fluid and manufacturing method thereof 失效
标题翻译：具有冷却流体通道的半导体装置及其制造方法
公开(公告)号：US07741159B2
公开(公告)日：2010-06-22
申请号：US12499408
申请日：2009-07-08
申请人： Hisato Oyamatsu
发明人： Hisato Oyamatsu
IPC分类号： H01L21/44
CPC分类号： H01L21/764 , H01L21/76229 , H01L21/76251 , H01L21/823412 , H01L21/823481 , H01L23/473 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a first diffusion region formed in the semiconductor substrate, a semiconductor element formed in the first diffusion region, and a channel formed in the first diffusion region to receive a cooling fluid.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底中的第一扩散区，形成在第一扩散区中的半导体元件和形成在第一扩散区中以接收冷却流体的沟道。

8. 发明授权

US07521300B2 Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate 失效
标题翻译：包括单晶层的半导体器件衬底和半导体器件衬底的制造方法
公开(公告)号：US07521300B2
公开(公告)日：2009-04-21
申请号：US11455735
申请日：2006-06-20
申请人： Hajime Nagano , Takashi Yamada , Tsutomu Sato , Ichiro Mizushima , Hisato Oyamatsu
发明人： Hajime Nagano , Takashi Yamada , Tsutomu Sato , Ichiro Mizushima , Hisato Oyamatsu
IPC分类号： H01L21/762
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.
摘要翻译：一种制造半导体器件基板的方法包括：通过电绝缘层在与半导体衬底的表面绝缘的半导体层上形成掩模层图案，根据掩模层的图案蚀刻半导体层，形成通向绝缘层，蚀刻具有小于绝缘层厚度的厚度的半导体衬底上的保护层，以形成覆盖沟槽侧表面的侧壁保护膜，从沟槽的底表面蚀刻绝缘层至半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。

9. 发明授权

US07018904B2 Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same 失效
公开(公告)号：US07018904B2
公开(公告)日：2006-03-28
申请号：US10921273
申请日：2004-08-19
申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
发明人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
IPC分类号： H01L21/76 , H01L21/20
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10832 , H01L27/10861 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

10. 发明申请

US20050121722A1 Semiconductor device having patterned SOI structure and method for fabricating the same 有权
标题翻译：具有图案化SOI结构的半导体器件及其制造方法
公开(公告)号：US20050121722A1
公开(公告)日：2005-06-09
申请号：US11036000
申请日：2005-01-18
申请人： Hisato Oyamatsu
发明人： Hisato Oyamatsu
IPC分类号： H01L21/66 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10861 , H01L27/1203
摘要： A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate, removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region, selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region, removing the second insulation film, polishing the second semiconductor layer in the third region using the second insulation film in the second region as a stopper after the second semiconductor layer is formed, and forming semiconductor elements on the first semiconductor layer and the second semiconductor layer after the second insulation film is removed.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的第一至第三区域中依次形成第一绝缘膜，第一半导体层和第二绝缘膜，去除第一绝缘膜，第一半导体层和在第一区域中的第二绝缘膜和第三区域中的第二绝缘膜，在半导体衬底的第一区域和第三区域中的第一半导体层上选择性地形成第二半导体层，去除第二绝缘膜，在形成第二半导体层之后，在第二区域中使用第二绝缘膜的第二半导体层作为阻挡层，在除去第二绝缘膜之后，在第一半导体层和第二半导体层上形成半导体元件。

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