专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07930575B2 Microcontroller for controlling power shutdown process 有权
标题翻译：用于控制电源关闭过程的微控制器
公开(公告)号：US07930575B2
公开(公告)日：2011-04-19
申请号：US11898145
申请日：2007-09-10
申请人： Yukari Suginaka , Toshifumi Hamaguchi , Yoshitaka Kitao , Shinya Muramatsu
发明人： Yukari Suginaka , Toshifumi Hamaguchi , Yoshitaka Kitao , Shinya Muramatsu
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3296 , Y02D10/128 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： A power supply unit is arranged between a CPU and a power supply device for supplying power to the CPU. Information necessary in proceeding with a program is evacuated from the CPU to an information holding unit. When a power shutdown factor is generated, a power supply control unit outputs a shutdown request signal to the CPU. The CPU, upon receiving the shutdown request signal, activates a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after the evacuation is completed. Upon receiving the evacuation completed signal, the power supply control unit outputs a power shutdown control signal to the power supply unit. Upon receiving the power shutdown control signal from the power supply control unit, the power supply unit shuts down power supply to the CPU.
摘要翻译：在CPU和供电装置之间设置电源单元，用于向CPU供电。执行程序所必需的信息从CPU撤出到信息保存单元。当产生电源关闭因素时，电源控制单元向CPU输出关闭请求信号。 CPU在接收到关闭请求信号后，激活电源关闭微程序，将执行程序所必需的信息撤出到信息保持单元，并且在完成撤离之后将撤离完成信号输出到电源控制单元。在接收到撤离完成信号时，电源控制单元向电源单元输出停电控制信号。在从电源控制单元接收到电源关闭控制信号时，电源单元关闭CPU的电源。

2. 发明申请

US20070101101A1 Microprocessor 审中-公开
标题翻译：微处理器
公开(公告)号：US20070101101A1
公开(公告)日：2007-05-03
申请号：US11584515
申请日：2006-10-23
申请人： Hiroyuki Odahara , Toshifumi Hamaguchi , Shinya Muramatsu
发明人： Hiroyuki Odahara , Toshifumi Hamaguchi , Shinya Muramatsu
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/30181
摘要： In a microprocessor that interprets instructions where a same instruction code can be interpreted as separate instructions with respectively different data lengths, a data length storage circuit that stores data length selection-use information is provided in a decoding unit. Instructions instructing storage to a general-purpose register, such storage of 8-bit immediate data to register R1, are set in advance as first-type instructions. Instructions that do not explicitly specify a data length, in other words, instructions whose processing targets are various lengths of data stored in the general-purpose register are set in advance as second-type instructions. When decoding a first-type instruction, the decoding unit updates the data length selection-use information in accordance with the first-type instruction. When decoding a second-type instruction, the decoding unit specifies the data length by referring to the data length selection-use information, and decodes the second-type instruction based on the specified data length.
摘要翻译：在解码指令的微处理器中，相同的指令代码可被解释为分别具有不同数据长度的单独指令，在解码单元中提供存储数据长度选择使用信息的数据长度存储电路。指令存储到通用寄存器的指令，将8位立即数据存储到寄存器R 1，作为第一类型指令被预先设置。没有明确指定数据长度的指令，换句话说，其处理目标是存储在通用寄存器中的各种长度的数据的指令被预先设置为第二类型指令。当解码第一类型指令时，解码单元根据第一类型指令来更新数据长度选择使用信息。当解码第二类型指令时，解码单元通过参考数据长度选择使用信息来指定数据长度，并且基于指定的数据长度对第二类型指令进行解码。

3. 发明授权

US06253305B1 Microprocessor for supporting reduction of program codes in size 有权
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US06253305B1
公开(公告)日：2001-06-26
申请号：US09226791
申请日：1999-01-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

4. 发明授权

US5966514A Microprocessor for supporting reduction of program codes in size 失效
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US5966514A
公开(公告)日：1999-10-12
申请号：US643947
申请日：1996-05-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

5. 发明申请

US20080065920A1 Microcontroller and arts related thereto 有权
标题翻译：微控制器及相关艺术
公开(公告)号：US20080065920A1
公开(公告)日：2008-03-13
申请号：US11898145
申请日：2007-09-10
申请人： Yukari Suginaka , Toshifumi Hamaguchi , Yoshitaka Kitao , Shinya Muramatsu
发明人： Yukari Suginaka , Toshifumi Hamaguchi , Yoshitaka Kitao , Shinya Muramatsu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3296 , Y02D10/128 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： A power supply unit is arranged between a CPU and a power supply device for supplying power to the CPU. Information necessary in proceeding with a program is evacuated from the CPU to an information holding unit. When a power shutdown factor is generated, a power supply control unit outputs a shutdown request signal to the CPU. The CPU, upon receiving the shutdown request signal, activates a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after the evacuation is completed. Upon receiving the evacuation completed signal, the power supply control unit outputs a power shutdown control signal to the power supply unit. Upon receiving the power shutdown control signal from the power supply control unit, the power supply unit shuts down power supply to the CPU.
摘要翻译：在CPU和供电装置之间设置电源单元，用于向CPU供电。执行程序所需的信息从CPU撤出到信息保存单元。当产生电源关闭因素时，电源控制单元向CPU输出关闭请求信号。 CPU在接收到关闭请求信号后，激活电源关闭微程序，将执行程序所必需的信息撤出到信息保持单元，并且在完成撤离之后将撤离完成信号输出到电源控制单元。在接收到撤离完成信号时，电源控制单元向电源单元输出停电控制信号。在从电源控制单元接收到电源关闭控制信号时，电源单元关闭CPU的电源。

6. 发明申请

US20080061894A1 Ring oscillator and semiconductor integrated circuit and electronic device including the same 失效
标题翻译：环形振荡器和半导体集成电路和电子设备包括相同
公开(公告)号：US20080061894A1
公开(公告)日：2008-03-13
申请号：US11892444
申请日：2007-08-23
申请人： Kazuhisa Raita , Ichiro Yamane , Yoshitaka Kitao , Toshifumi Hamaguchi , Takahiro Inauchi
发明人： Kazuhisa Raita , Ichiro Yamane , Yoshitaka Kitao , Toshifumi Hamaguchi , Takahiro Inauchi
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03L1/00 , H03L7/0995
摘要： A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.
摘要翻译：差分放大电路包括：由第一和第二晶体管组成的差分晶体管对; 连接到一个端子处的第一和第二晶体管的连接点的第一电阻和另一个端子处的第一电压节点的第一电阻; 分别设置在第一和第二晶体管之间的第二和第三电阻和第二电压节点; 以及分别连接到第二和第三电阻的第一和第二无源电路，无源电路的负载特性根据提供的控制信号而变化。环形振荡器由以循环连接的多个这样的差分放大器电路组成。

7. 发明申请

US20070182499A1 Oscillation circuit 审中-公开
标题翻译：振荡电路
公开(公告)号：US20070182499A1
公开(公告)日：2007-08-09
申请号：US11703647
申请日：2007-02-08
申请人： Katsushi Wakai , Ichiro Yamane , Toshifumi Hamaguchi , Kazuhisa Raita
发明人： Katsushi Wakai , Ichiro Yamane , Toshifumi Hamaguchi , Kazuhisa Raita
IPC分类号： H03B5/20
CPC分类号： H03K4/502
摘要： A first comparator outputs a first signal indicative that a voltage determined according to the amount of charge stored in a first capacitor has reached a first reference voltage. A second comparator outputs a second signal indicative that a voltage determined according to the amount of charge stored in a second capacitor has reached a second reference voltage. An RS flip flop circuit is shifted to a set state by one of the first signal and the second signal and shifted to a reset state by the other signal. When the RS flip flop circuit is in the set state, the first capacitor is in a charge state, and the second capacitor is in a discharge state. When the RS flip flop circuit is in the reset state, the first capacitor is in a discharge state, and the second capacitor is in a charge state.
摘要翻译：第一比较器输出指示根据存储在第一电容器中的电荷量确定的电压已经达到第一参考电压的第一信号。第二比较器输出指示根据存储在第二电容器中的电荷量确定的电压已经达到第二参考电压的第二信号。 RS触发器电路通过第一信号和第二信号中的一个移位到设置状态，并通过另一个信号移位到复位状态。当RS触发电路处于置位状态时，第一电容器处于充电状态，第二电容器处于放电状态。当RS触发电路处于复位状态时，第一电容器处于放电状态，第二电容器处于充电状态。

8. 发明授权

US07042298B2 Oscillator circuit and oscillation stabilizing method 失效
标题翻译：振荡电路和振荡稳定方法
公开(公告)号：US07042298B2
公开(公告)日：2006-05-09
申请号：US10877987
申请日：2004-06-29
申请人： Yoshimasa Nakahi , Toshifumi Hamaguchi
发明人： Yoshimasa Nakahi , Toshifumi Hamaguchi
IPC分类号： H03B5/32 , H03L1/00 , H03L5/00
CPC分类号： H03K3/02315 , H03B5/364 , H03K3/014
摘要： An oscillator circuit and an oscillation stabilizing method are provided that can improve the productivity of products, stabilize an oscillating operation, and achieve more stable operations for a system supplied with oscillation output. An output from a variable capability oscillator circuit is received by two inverters having different threshold values. Regarding voltage values that are exceeded when oscillation is stabilized in the inverters, the boundaries of the voltage values are set as an astable boundary and an astable boundary which are the threshold values of the inverters, outputs from the inverters are counted by a stable oscillation period shortening circuit based on the timing of a clock used for the system, and the capability of the variable capability oscillator circuit is maximized until oscillation is stabilized, thereby further shortening a stable oscillation period.
摘要翻译：提供振荡电路和振荡稳定方法，其可以提高产品的生产率，稳定振荡操作，并且对于提供有振荡输出的系统实现更稳定的操作。来自可变能力振荡器电路的输出由具有不同阈值的两个反相器接收。关于在逆变器中稳定振荡时超过的电压值，电压值的边界被设定为作为反相器的阈值的不稳定边界和不稳定边界，来自反相器的输出由稳定的振荡周期基于用于系统的时钟的定时的缩短电路，并且可变能量振荡器电路的能力最大化直到振荡稳定，从而进一步缩短稳定的振荡周期。

9. 发明申请

US20090249032A1 INFORMATION APPARATUS 审中-公开
标题翻译：信息设备
公开(公告)号：US20090249032A1
公开(公告)日：2009-10-01
申请号：US12392184
申请日：2009-02-25
申请人： Takashi Nishihara , Toshifumi Hamaguchi
发明人： Takashi Nishihara , Toshifumi Hamaguchi
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F5/015 , G06F7/768
摘要： An information apparatus comprises: a barrel shifter composed of a bidirectional 1-bit shifter, . . . , and a bidirectional 24-bit shifter which are connected in series; a control unit for outputting an endian conversion control signal SE indicating one of a shift operation and endian conversion; an endian conversion unit for generating data by endian conversion using data obtained by performing a shift operation in the bidirectional 8-bit shifter and the bidirectional 24-bit shifter; and a selector for selecting, when the endian conversion control signal SE indicates a shift operation, data outputted from the bidirectional 24-bit shifter, and selecting, when the endian conversion control signal SE indicates endian conversion, the data outputted from the endian conversion unit.
摘要翻译：信息装置包括：由双向1位移位器组成的桶形移位器。。。，以及串联连接的双向24位移位器; 控制单元，用于输出表示移位操作和字节序转换中的一个的端序转换控制信号SE; 用于通过在双向8位移位器和双向24位移位器中执行移位操作获得的数据通过端序转换来生成数据的端序转换单元; 以及选择器，用于当端段转换控制信号SE指示移位操作时，选择从双向24位移位器输出的数据，并且当端段转换控制信号SE指示端序转换时，选择从端转换单元输出的数据。

10. 发明申请

US20080082802A1 Microcomputer debugging system 审中-公开
标题翻译：微机调试系统
公开(公告)号：US20080082802A1
公开(公告)日：2008-04-03
申请号：US11905228
申请日：2007-09-28
申请人： Shinya Muramatsu , Toshifumi Hamaguchi
发明人： Shinya Muramatsu , Toshifumi Hamaguchi
IPC分类号： G06F9/00
CPC分类号： G06F11/3652
摘要： A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the plurality of debug modes, and is allowed to shift to the interruption program during the debugging operation in another debug mode.
摘要翻译：一种能够执行多个调试模式的微型计算机调试系统，其中在所述多个调试模式之一中的调试操作期间不允许处理转换到中断程序，并且在调试操作期间被允许切换到中断程序在另一个调试模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式