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1. 发明授权

US06253305B1 Microprocessor for supporting reduction of program codes in size 有权
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US06253305B1
公开(公告)日：2001-06-26
申请号：US09226791
申请日：1999-01-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

2. 发明授权

US5966514A Microprocessor for supporting reduction of program codes in size 失效
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US5966514A
公开(公告)日：1999-10-12
申请号：US643947
申请日：1996-05-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

3. 发明授权

US5649229A Pipeline data processor with arithmetic/logic unit capable of performing different kinds of calculations in a pipeline stage 失效
标题翻译：具有算术/逻辑单元的管道数据处理器能够在流水线阶段执行不同类型的计算
公开(公告)号：US5649229A
公开(公告)日：1997-07-15
申请号：US419957
申请日：1995-04-10
申请人： Toshimichi Matsuzaki , Nobuo Higaki , Masashi Deguchi
发明人： Toshimichi Matsuzaki , Nobuo Higaki , Masashi Deguchi
IPC分类号： G06F9/30 , G06F9/312 , G06F9/318 , G06F9/32 , G06F9/38 , G06F12/02 , G06F15/78 , G06F13/00
CPC分类号： G06F9/30 , G06F15/7832 , G06F9/30043 , G06F9/30058 , G06F9/30181
摘要： The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.
摘要翻译：本发明的数据处理器在写入寄存器的周期期间通过未使用的总线传送地址寄存器和程序寄存器的内容，并且在一个周期中执行需要地址计算的加载指令或存储指令，尽管处理器具有两个总线和一个算术/逻辑单元。此外，数据处理器通过将通用寄存器功能划分为四个地址寄存器和四个数据寄存器来分配寄存器之间的基本算术指令和加载/存储指令，其具有一个字节的基本指令字长度。

4. 发明授权

US5301289A Cache device for supplying a fixed word length of a variable instruction code and instruction fetch device 失效
标题翻译：用于提供可变指令代码和指令获取装置的固定字长的缓存装置
公开(公告)号：US5301289A
公开(公告)日：1994-04-05
申请号：US80048
申请日：1993-06-21
申请人： Masato Suzuki , Masashi Deguchi , Takashi Sakao , Toshimichi Matsuzaki
发明人： Masato Suzuki , Masashi Deguchi , Takashi Sakao , Toshimichi Matsuzaki
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3806 , G06F12/0875 , G06F9/3844
摘要： An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address. At the time of reading an instruction, first, a pair having an address of a branch instruction which address is the nearest to a head address of an instruction string to be read out is selected from a plurality of pairs, each pair including an address of a branch instruction which address is in a predetermined address range including the instruction string to be read out, or each pair of the plurality of pairs including a value obtained by subtracting a given value from the address of the branch instruction. Then, a branch destination address is selected and output from the pair which is selected first from the plurality of pairs.
摘要翻译：指令提取设备包括高速缓存设备和分支历史表中的一个或两个。高速缓存设备存储多对，每对包括分成最小单位指令和指令串地址的指令串。在读取指令时，由至少两对的每个最小单位指令选择并输出指令串。分支历史表存储多对，每对包括分支目的地地址和分支指令的地址集合，以及通过从地址中减去给定值而获得的值。在读取指令时，首先从多个对中选择具有地址与要读出的指令串的头地址最接近的分支指令的地址的一对，每对包括地址在包括要读出的指令串的预定地址范围内的分支指令，或包括通过从分支指令的地址中减去给定值而获得的值的每对对。然后，从多个对中首先选择的一对中选择并输出分支目的地地址。

5. 发明授权

US5440701A For shortening an instruction code length 失效
标题翻译：缩短指令码长度
公开(公告)号：US5440701A
公开(公告)日：1995-08-08
申请号：US932652
申请日：1992-08-20
申请人： Toshimichi Matsuzaki , Masashi Deguchi
发明人： Toshimichi Matsuzaki , Masashi Deguchi
IPC分类号： G06F9/34 , G06F9/30 , G06F9/318
CPC分类号： G06F9/30149 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3017 , G06F9/30181
摘要： Disclosed is a data processing apparatus comprising a decode device for decoding an instruction code including an operation code and two register designation codes and an instruction execution device for executing appropriate process according to the results decoded by the decode device, wherein the instruction execution device executes a first process when the two register designation codes are different from each other and executes a second process when they are equal.
摘要翻译：公开了一种数据处理装置，包括用于对包括操作码和两个寄存器指定码的指令码进行解码的解码装置，以及用于根据解码装置解码的结果执行适当处理的指令执行装置，其中指令执行装置执行当两个寄存器指定码彼此不同时执行第一处理，并且当它们相等时执行第二处理。

6. 发明授权

US5418969A Low power consumption microprocessor 失效
标题翻译：低功耗微处理器
公开(公告)号：US5418969A
公开(公告)日：1995-05-23
申请号：US278102
申请日：1994-07-20
申请人： Toshimichi Matsuzaki , Masashi Deguchi
发明人： Toshimichi Matsuzaki , Masashi Deguchi
IPC分类号： G06F15/16 , G06F1/04 , G06F1/32 , G06F9/38 , G06F15/177 , G06F15/78 , G06F1/08 , G06F1/18
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3287 , G06F9/3869 , Y02B60/1217 , Y02B60/1282
摘要： A microprocessor which reduces power consumption by monitoring the operating status of a plurality of operating units in the microprocessor to extract the unit which is recently most infrequently used to change the frequency of the operating clock supplied thereto in steps.
摘要翻译：一种微处理器，其通过监视微处理器中的多个操作单元的操作状态来降低功耗，以提取最近最不常用的单元，以逐步改变提供给它的工作时钟的频率。

7. 发明授权

US5197136A Processing system for branch instruction 失效
标题翻译：分支指令处理系统
公开(公告)号：US5197136A
公开(公告)日：1993-03-23
申请号：US614680
申请日：1990-11-19
申请人： Kozo Kimura , Tokuzo Kiyohara , Toshimichi Matsuzaki
发明人： Kozo Kimura , Tokuzo Kiyohara , Toshimichi Matsuzaki
IPC分类号： G06F9/38
CPC分类号： G06F9/3804
摘要： A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.
摘要翻译：存储器保存包括分支指令和相应的分支目的地指令的指令。这些指令从存储器顺序取出到解码器。解码器顺序地对获取的指令进行解码并从相应的指令导出命令。这些命令从解码器顺序传送到执行单元。执行单元依次执行传送命令。解码器用于检测分支指令。当检测到分支指令时，正常指令取出处理被中断，并且分支目的地指令被迅速地提取到解码器。解码器防止转移指令的命令被传送到执行单元。

8. 发明授权

US5237666A Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction 失效
标题翻译：装置使用预先指定的目标地址和目标地址存储在历史表中以预定目标指令
公开(公告)号：US5237666A
公开(公告)日：1993-08-17
申请号：US451252
申请日：1989-12-15
申请人： Masato Suzuki , Masahi Deguchi , Yukinobu Nishikawa , Toshimichi Matsuzaki , Masaya Miyazaki , Takashi Sakao
发明人： Masato Suzuki , Masahi Deguchi , Yukinobu Nishikawa , Toshimichi Matsuzaki , Masaya Miyazaki , Takashi Sakao
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/3806 , G06F9/3844
摘要： This data processor makes zero the execution clock count of a branch instruction, a compare instruction, or a compare instruction and following branch instruction when a series of instructions executed in the past is again executed. The data processor of this invention is provided with a history storage unit which stores as its address tag the address of an instruction executed before the branch instruction or compare instruction, and stores the address of an instruction to be executed next the branch or compare instruction or both instruction code of an instruction to be executed next the branch or compare instruction and an address used for pre-fetching an instruction following the instruction code. While the instruction before the branch or compare instruction is decoded, the history storage unit is searched to obtain an instruction to be next executed. The obtained instruction is executed immediately after the execution of the instruction immediately before the branch or compare instruction.

9. 发明授权

US5481679A Data processing apparatus having bus switches for selectively connecting buses to improve data throughput 失效
标题翻译：具有用于选择性地连接总线以提高数据吞吐量的总线开关的数据处理装置
公开(公告)号：US5481679A
公开(公告)日：1996-01-02
申请号：US121799
申请日：1993-09-15
申请人： Nobuo Higaki , Toshimichi Matsuzaki
发明人： Nobuo Higaki , Toshimichi Matsuzaki
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F15/78 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4027 , G06F13/28 , G06F15/7817
摘要： A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed. Hence, data throughput on the buses can be improved and the load capacity can be reduced, which leads to heightening of the clock frequency.
摘要翻译：描述了一种数据处理装置，包括连接指令存储单元和指令准备单元的第一总线，连接指令执行单元和数据存储单元的第二总线，总线选择性地电连接和断开第一和第二总线，以及控制单元，其响应于指令准备单元和指令执行单元的操作来控制总线开关的操作。当通过总线开关连接第一和第二总线时，可以执行从指令准备单元到数据存储单元的访问以及从指令执行单元到指令存储单元的访问。另一方面，当总线未连接时，可以同时执行从指令准备单元的指令和来自指令执行单元的数据访问。因此，可以提高总线上的数据吞吐量，并且可以减小负载能力，从而导致时钟频率的提高。

10. 发明授权

US5202967A Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction 失效
标题翻译：数据处理装置，用于执行可变字长度指令的并行解码和并行执行
公开(公告)号：US5202967A
公开(公告)日：1993-04-13
申请号：US916804
申请日：1992-07-20
申请人： Toshimichi Matsuzaki , Takashi Sakao
发明人： Toshimichi Matsuzaki , Takashi Sakao
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/30149 , G06F9/3822 , G06F9/3842
摘要： A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.
摘要翻译：一种以可变字长指令格式并行地解码和执行指令的数据处理装置。使用多个解码器，其中当主指令解码器正在解码指令时，检测到下一条指令的并行解码的概率，使得主指令解码器和辅助指令解码器解码可变字长度指令和固定字长指令，分别以并行方式。固定字长的条件分支指令和可变字长度的后续指令以并行方式被解码和执行，以增加执行条件转移指令的速度。

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