专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

US20230317508A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PRE-CLEANING TREATMENT 审中-公开
公开(公告)号：US20230317508A1
公开(公告)日：2023-10-05
申请号：US17708146
申请日：2022-03-30
申请人： NANYA TECHNOLOGY CORPORATION
发明人： WEI-CHEN PAN , CHUN-WEI WANG
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76221 , H01L21/76235 , H01L21/02043
摘要： The present application discloses a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes forming a first dielectric layer on a substrate; forming a feature opening to exposing the substrate; performing a pre-cleaning treatment including a pre-cleaning solution to the feature opening; performing a cleaning process to the feature opening; and forming a conductive feature in the feature opening. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor.

2. 发明公开

US20230207666A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20230207666A1
公开(公告)日：2023-06-29
申请号：US18080870
申请日：2022-12-14
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Huan Wang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762
CPC分类号： H01L29/66681 , H01L29/7816 , H01L29/0653 , H01L21/76235
摘要： A method of manufacturing a semiconductor device having a combination structure of a horizontal oxide layer structure and a vertical oxide layer structure, can include: etching from an upper surface of the semiconductor substrate to inside of the semiconductor substrate to form a trench; depositing oxides in the trench to form the vertical oxide layer structure; etching the vertical oxide layer structure from an upper surface thereof to decrease height of the vertical oxide layer structure, and to make a top surface of the vertical oxide layer structure be below the upper surface of the semiconductor substrate, in order to expose side surfaces of the trench; and forming, by an oxidation process, the horizontal oxide layer structure to cover part of the upper surface of the semiconductor substrate and the upper surface of the vertical oxide layer structure.

3. 发明授权

US09978635B2 Method and apparatus for semiconductor device with reduced device footprint 有权
公开(公告)号：US09978635B2
公开(公告)日：2018-05-22
申请号：US14242269
申请日：2014-04-01
申请人： Vanguard International Semiconductor Corporation
发明人： Chien-Hsien Song
IPC分类号： H01L21/762 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/06 , H01L21/311
CPC分类号： H01L21/76235 , H01L21/31144 , H01L29/0653 , H01L29/41766 , H01L29/42368 , H01L29/66659
摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor layer, and a trench formed in a top surface of the semiconductor layer. The trench has a bottom surface and a sidewall. The semiconductor device further includes source and drain regions. One of the source and drain regions may be disposed at the bottom surface of the trench, and the other may be disposed at the top surface of the semiconductor layer, or vice versa. Alternatively, both source and drain regions may be disposed at the bottom surface of the trench. The semiconductor device may further include a first insulator disposed in the trench and in between the source and drain regions. The semiconductor device may further include a second insulator disposed between first insulator and the source region. The semiconductor device may further include a conductive member that disposed on the first insulator, or on the first and second insulators.

4. 发明授权

US09646871B2 Semiconductor structure with shallow trench isolation and manufacturing method thereof 有权
公开(公告)号：US09646871B2
公开(公告)日：2017-05-09
申请号：US14337562
申请日：2014-07-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Che-Cheng Chang , Tung-Wen Cheng , Jui Fu Hseih , Mu-Tsang Lin
IPC分类号： H01L29/76 , H01L21/762 , H01L29/06 , H01L29/78
CPC分类号： H01L21/76235 , H01L21/76232 , H01L29/0649 , H01L29/785
摘要： A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

5. 发明申请

US20160027684A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20160027684A1
公开(公告)日：2016-01-28
申请号：US14337562
申请日：2014-07-22
申请人： Taiwan Semiconductor Manufacturing Company Ltd.
发明人： CHE-CHENG CHANG , TUNG-WEN CHENG , JUI FU HSEIH , MU-TSANG LIN
IPC分类号： H01L21/762 , H01L29/06 , H01L29/78
CPC分类号： H01L21/76235 , H01L21/76232 , H01L29/0649 , H01L29/785
摘要： A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.
摘要翻译：半导体结构包括半导体衬底和浅沟槽隔离（STI）。 STI包括与半导体衬底接口的侧壁。 STI从半导体衬底的底部挤出，并且STI包括接触半导体衬底的底部的底面; 与底面相对的顶面。底面包括大于顶面宽度的宽度。

6. 发明授权

US09105687B1 Method for reducing defects in shallow trench isolation 有权
标题翻译：减少浅沟槽隔离缺陷的方法
公开(公告)号：US09105687B1
公开(公告)日：2015-08-11
申请号：US14254523
申请日：2014-04-16
申请人： NXP B.V.
发明人： Jerome Dubois , Piet Wessels , Gaurav Singh Bisht , Jayaraj Thillaigovindan , Eric Ooms , Naveen Agrawal
IPC分类号： H01L21/762 , H01L21/321 , H01L21/306
CPC分类号： H01L21/76235 , H01L21/30604 , H01L21/3065 , H01L21/3212 , H01L21/76224 , H01L21/76232 , H01L21/764
摘要： A method of manufacturing a semiconductor device includes forming a trench that includes a needle defect, depositing a high density plasma oxide over the trench including the needle defect, removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch, and after the step of applying the oxide etch, etching back the needle defect by applying a polysilicon etch.
摘要翻译：一种制造半导体器件的方法包括形成包括针缺陷的沟槽，在包括针缺陷的沟槽上沉积高密度等离子体氧化物，通过施加一个或多个针孔缺陷来去除部分高密度氧化物和衬垫氧化物氧化物蚀刻，并且在施加氧化物蚀刻的步骤之后，通过施加多晶硅蚀刻来回蚀针缺陷。

7. 发明申请

US20150200300A1 SEMICONDUCTOR DEVICE AND FORMATION THEREOF 有权
标题翻译：半导体器件及其形成
公开(公告)号：US20150200300A1
公开(公告)日：2015-07-16
申请号：US14155793
申请日：2014-01-15
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Kuo-Cheng Ching , Chih-Hao Wang , Zhiqiang Wu , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L21/02 , H01L29/16 , H01L29/06 , H01L29/66 , H01L21/762
CPC分类号： H01L29/7851 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/76224 , H01L21/76235 , H01L29/0638 , H01L29/0649 , H01L29/16 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.
摘要翻译：本文提供半导体器件和形成方法。半导体器件包括具有沿着第一平面延伸的第一壁的鳍片，鳍片包括在第一平面的第一侧上限定第一沟槽的掺杂区域。电介质设置在第一沟槽内，使得电介质与电介质的第一端和电介质的第二端之间的第一沟槽接触。第一端与第一平面分开第一距离。与包括不包括设置在沟槽内的电介质的翅片的FinFet相比，设置在沟槽内的电介质增加了相邻散热片的通道部分的隔离，从而减小了FinFet的漏电流。

8. 发明申请

US20150097248A1 SHALLOW TRENCH ISOLATION 有权
标题翻译：浅层分离
公开(公告)号：US20150097248A1
公开(公告)日：2015-04-09
申请号：US14549559
申请日：2014-11-21
申请人： UNITED MICROELECTRONICS CORP.
发明人： En-Chiuan Liou , Po-Chao Tsao , Chia-Jui Liang , Jia-Rong Wu
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76235 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649
摘要： The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.
摘要翻译：半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

9. 发明授权

US07989308B2 Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher voltages 有权
标题翻译：创建介质绝缘的技术沟槽，包括用于允许更高电压的圆形边缘
公开(公告)号：US07989308B2
公开(公告)日：2011-08-02
申请号：US10599726
申请日：2005-04-07
申请人： Ralf Lerner , Uwe Eckoldt , Thomas Oetzel
发明人： Ralf Lerner , Uwe Eckoldt , Thomas Oetzel
IPC分类号： H01L27/12
CPC分类号： H01L21/76235
摘要： The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.
摘要翻译：本发明的目的是将低电压逻辑元件和高压功率元件集成在同一个硅电路中。所述目的通过借助于隔离沟槽（10）彼此具有不同电位的介电芯片区域实现。为了防止隔离沟底部的尖锐边缘处的电压上升，所述边缘以简单的工艺被倒圆，绝缘层（2）的一部分被各向同性地蚀刻。

10. 发明授权

US07759214B2 Semiconductor including STI and method for manufacturing the same 失效
标题翻译：包括STI的半导体及其制造方法
公开(公告)号：US07759214B2
公开(公告)日：2010-07-20
申请号：US11505727
申请日：2006-08-17
申请人： Suh Byoung Yoon
发明人： Suh Byoung Yoon
IPC分类号： H01L21/02
CPC分类号： H01L21/76232 , H01L21/76235
摘要： Provided is a semiconductor device and method of making, incorporating a trench having rounded edges. According to an embodiment, a pad oxide layer, nitride layer, and TEOS layer are sequentially formed on a substrate. The TEOS layer, nitride layer, and pad oxide layer are dry-etched using a photosensitive layer pattern as a mask. After removing the photosensitive layer pattern, a trench is formed by dry-etching the substrate using the etched TEOS layer, nitride layer, and pad oxide layer as a mask. A portion of the pad oxide layer is pullback-etched, resulting in a first rounding of the trench. A portion of the etched nitride layer is pullback-etched and a portion of the etched TEOS layer is pullback-etched. The upper corner of the trench of the substrate is dry-etched using the pullback-etched TEOS layer, nitride layer, and pad oxide layer as a mask, resulting in a second rounding of the trench.
摘要翻译：提供了一种半导体器件和制造方法，结合具有圆形边缘的沟槽。根据实施例，衬底氧化物层，氮化物层和TEOS层依次形成在衬底上。使用感光层图案作为掩模来干蚀刻TEOS层，氮化物层和焊盘氧化物层。在去除感光层图案之后，通过使用蚀刻的TEOS层，氮化物层和焊盘氧化物层作为掩模对基板进行干蚀刻来形成沟槽。衬垫氧化物层的一部分被回拉蚀刻，导致沟槽的第一舍入。蚀刻的氮化物层的一部分被回拉蚀刻，并且蚀刻的TEOS层的一部分被回拉刻蚀。使用回拉蚀刻的TEOS层，氮化物层和衬垫氧化物层作为掩模来干蚀刻衬底的沟槽的上角，导致沟槽的第二个圆化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式