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1. 发明授权

US07312125B1 Fully depleted strained semiconductor on insulator transistor and method of making the same 有权
标题翻译：绝缘子晶体管的全耗尽应变半导体及其制造方法
公开(公告)号：US07312125B1
公开(公告)日：2007-12-25
申请号：US10773026
申请日：2004-02-05
申请人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/66553 , H01L29/66621 , H01L29/7848 , H01L29/78621 , H01L29/78684 , Y10S438/938
摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.
摘要翻译：集成电路包括多层。可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。可以结合两个基板或晶片以形成多个层。应变半导体层可以在硅锗层和掩埋氧化物层之间。氢注入可以提供断开界面以从硅锗层去除硅衬底。

2. 发明授权

US06432805B1 Co-deposition of nitrogen and metal for metal silicide formation 有权
标题翻译：用于金属硅化物形成的氮和金属的共沉积
公开(公告)号：US06432805B1
公开(公告)日：2002-08-13
申请号：US09783620
申请日：2001-02-15
申请人： Eric N. Paton , Minh Van Ngo , Paul R. Besser
发明人： Eric N. Paton , Minh Van Ngo , Paul R. Besser
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.
摘要翻译：通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

3. 发明授权

US06605513B2 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权
标题翻译：使用一步快速热退火工艺和后端加工形成硅化镍的方法
公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译：自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。去除未反应的镍。然后将电介质层沉积在高电阻镍硅化物区域上。在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

4. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

5. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

6. 发明授权

US06660621B1 Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation 失效
标题翻译：在具有从气体前体沉积的硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗
公开(公告)号：US06660621B1
公开(公告)日：2003-12-09
申请号：US10163461
申请日：2002-06-07
申请人： Paul R. Besser , Minh Van Ngo
发明人： Paul R. Besser , Minh Van Ngo
IPC分类号： H01L213205
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/665
摘要： A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.
摘要翻译：在半导体晶片中形成超浅结的方法形成栅极和源极/漏极结，其在栅极和源极/漏极结上的第一金属硅化物区具有上表面。这些第一金属硅化物区域具有较高的电阻率。通过等离子体增强化学气相沉积（PECVD）将非晶硅沉积在第一金属硅化物区域上。 PECVD工艺可以是较低压力的沉积工艺，在多个工位上执行以在多层中形成非晶硅层。这就形成了跨越晶片的更均匀的非晶硅层和不同的图案化密度，从而提高了器件性能和特性。然后通过第一金属硅化物区域和通过PECVD工艺沉积的非晶硅的扩散反应，进行退火以形成较低电阻率的第二金属硅化物区域。

7. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

8. 发明授权

US06221794B1 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines 失效
标题翻译：降低半导体互连线中应力诱发空隙的发生率的方法
公开(公告)号：US06221794B1
公开(公告)日：2001-04-24
申请号：US09208596
申请日：1998-12-08
申请人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo
发明人： Suzette K. Pangrle , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , C23C16/308 , H01L21/0276 , H01L21/76834 , H01L21/76885
摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During processing the deposition temperature is reduced to under 400 degrees Celsius, specifically temperatures in the range of about 350 degrees Celsius to about 380 degrees, Celsius, resulting in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.
摘要翻译：在基板的微电路互连线上形成层间电介质（ILD）涂层的方法中，通过使用等离子体增强化学气相沉积形成SiON层。使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。等离子体反应形成沉积在半导体衬底上的SiON。在加工过程中，沉积温度降低至400摄氏度以下，特别是约350摄氏度至约380摄氏度的温度，导致底层互连线中应力引起的空隙的发生率基本上降低。此外，在沉积期间，对沉积温度和工艺压力进行微调，以控制SiON层的光学特性。测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。一旦形成了ILD，底物就可以进行进一步的处理。

9. 发明授权

US07217660B1 Method for manufacturing a semiconductor component that inhibits formation of wormholes 有权
标题翻译：制造抑制虫洞形成的半导体部件的方法
公开(公告)号：US07217660B1
公开(公告)日：2007-05-15
申请号：US11109964
申请日：2005-04-19
申请人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
发明人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
IPC分类号： H01L21/22
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L29/6659
摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.
摘要翻译：一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。在设置在半导体衬底上的电介质层中形成接触开口。接触开口露出半导体衬底的一部分。在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

10. 发明授权

US07049666B1 Low power pre-silicide process in integrated circuit technology 有权
标题翻译：集成电路技术中的低功耗预硅化工艺
公开(公告)号：US07049666B1
公开(公告)日：2006-05-23
申请号：US10859286
申请日：2004-06-01
申请人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
发明人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L29/94 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成一个薄的绝缘层。在薄绝缘层和栅极上形成硅化物。在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

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