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1. 发明授权

US09972505B2 Semiconductor device and its manufacturing method 有权
公开(公告)号：US09972505B2
公开(公告)日：2018-05-15
申请号：US14943900
申请日：2015-11-17
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Masahiro Matsumoto , Kazuyoshi Maekawa , Yuichi Kawano
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00 , H01L23/532 , H01L21/768 , H01L23/31 , H01L23/525
CPC分类号： H01L21/4817 , H01L21/76852 , H01L23/3121 , H01L23/525 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2221/1078 , H01L2224/02166 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05008 , H01L2224/05075 , H01L2224/05548 , H01L2224/05664 , H01L2224/0612 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45644 , H01L2224/45664 , H01L2224/48247 , H01L2224/48465 , H01L2924/014 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

2. 发明授权

US09490210B2 Electrical interconnection structure and fabrication method thereof 有权
标题翻译：电互连结构及其制造方法
公开(公告)号：US09490210B2
公开(公告)日：2016-11-08
申请号：US14657465
申请日：2015-03-13
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Zhongshan Hong
IPC分类号： H01L23/52 , H01L23/532 , H01L21/02 , H01L21/027 , H01L21/3213 , H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L23/53238 , H01L21/0214 , H01L21/02164 , H01L21/0276 , H01L21/32135 , H01L21/32136 , H01L21/32139 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76852 , H01L21/76864 , H01L21/76877 , H01L21/76883 , H01L21/76885 , H01L21/76892 , H01L21/76897 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.
摘要翻译：提供了互连结构制造方法。该方法包括提供基板; 形成具有第一厚度并具有第一晶格结构和第一晶粒尺寸的导电膜，其中所述第一厚度大于所述第一晶粒尺寸; 并且执行退火处理以将导电膜的第一晶格结构改变为第二晶格结构并将第一晶粒尺寸改变为第二晶粒尺寸。第二晶粒尺寸大于第一晶粒尺寸，并且第一厚度大于或等于第二晶粒尺寸。该方法还包括导电膜的蚀刻部分以形成至少一个导电层; 蚀刻所述导电层的部分以在所述导电层中形成深度小于所述第一厚度的至少一个沟槽，以形成电互连线和导电通孔; 以及形成覆盖所述基板，所述导电层的侧壁和所述沟槽的电介质层。

3. 发明授权

US08232638B2 Interconnection structure having oxygen trap pattern in semiconductor device 失效
标题翻译：在半导体器件中具有氧阱图案的互连结构
公开(公告)号：US08232638B2
公开(公告)日：2012-07-31
申请号：US12195315
申请日：2008-08-20
申请人： Young-Tae Ma , In-Sun Park , Dong-Jo Kang , Hyun-Seok Lim , Do-Hyung Kim
发明人： Young-Tae Ma , In-Sun Park , Dong-Jo Kang , Hyun-Seok Lim , Do-Hyung Kim
IPC分类号： B32B15/00
CPC分类号： H01L21/7685 , H01L21/76805 , H01L21/76814 , H01L21/76888 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , Y10T428/31678 , H01L2924/00
摘要： An interconnection structure having an oxygen trap pattern in a semiconductor device, and a method of fabricating the same are provided. The interconnection structure includes a lower interlayer insulating layer formed on a semiconductor substrate. A metal layer pattern and a capping layer pattern are sequentially stacked on the lower interlayer insulating layer. An oxygen trap pattern is disposed on the capping layer pattern and includes a conductive oxygen trap pattern.
摘要翻译：提供了一种在半导体器件中具有氧阱图案的互连结构及其制造方法。互连结构包括形成在半导体衬底上的下层间绝缘层。金属层图案和覆盖层图案依次层叠在下层间绝缘层上。氧气阱图案设置在覆盖层图案上并且包括导电氧阱图案。

4. 发明申请

US20100255611A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100255611A1
公开(公告)日：2010-10-07
申请号：US12818279
申请日：2010-06-18
申请人： Wensheng Wang
发明人： Wensheng Wang
IPC分类号： H01L21/02
CPC分类号： H01L21/7687 , H01L21/2855 , H01L21/32051 , H01L21/76826 , H01L21/76834 , H01L21/76856 , H01L28/55 , H01L28/65 , H01L2221/1078
摘要： The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film.
摘要翻译：本发明提供一种半导体器件，其特征如下。半导体器件包括：形成在半导体衬底之上并在杂质扩散区上方设置有空穴的层间绝缘膜; 导电插塞，其形成在所述孔中并电连接到所述杂质扩散区; 形成在所述导电插塞和所述导电插塞周围的所述层间绝缘膜上的导电氧阻隔膜; 形成在导电氧阻隔膜上的导电性防扩散膜; 以及电容器，其具有形成在导电性防扩散膜上并在上表面露出铂或钯的下部电极，由铁电体材料制成的电容器电介质膜和上部电极。导电性防扩散膜由防止电容电介质膜的构成元素扩散的非氧化物导电材料构成。

5. 发明申请

US20100052178A1 Semiconductor Device and Method for Making Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100052178A1
公开(公告)日：2010-03-04
申请号：US12201888
申请日：2008-08-29
申请人： Dirk Meinhold , Heinrich Koerner , Wolfgang Dickenscheid
发明人： Dirk Meinhold , Heinrich Koerner , Wolfgang Dickenscheid
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76834 , H01L21/76849 , H01L21/7685 , H01L21/76888 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
摘要翻译：一个或多个实施例涉及一种半导体器件，其包括：包括侧壁的导电层; 导电覆盖层，其设置在所述导电层上并且横向延伸超过所述导电层的所述侧壁的横向突出端; 以及与导电覆盖层电接触的导电通孔。

6. 发明授权

US07585761B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07585761B2
公开(公告)日：2009-09-08
申请号：US11486149
申请日：2006-07-14
申请人： Shunpei Yamazaki , Mitsuaki Osame
发明人： Shunpei Yamazaki , Mitsuaki Osame
IPC分类号： H01L21/4763
CPC分类号： G02F1/136286 , G02F2001/136295 , H01L21/76838 , H01L21/76841 , H01L2221/1078
摘要： It is an object of the present invention to suppress an influence of voltage drop due to wiring resistance to make an image quality of a display device uniform. In addition, it is also an object of the present invention to suppress delay due to a wiring for electrically connecting a driving circuit portion to an input/output terminal to improve an operation speed in the driving circuit portion.In the present invention, a wiring including copper for realizing lowered wiring resistance, subjected to microfabrication, is used as a wiring used for a semiconductor device and a barrier conductive film for preventing diffusion of copper is provided for a TFT as a part of the wiring including copper to form the wiring including copper without diffusion of copper into a semiconductor layer of the TFT. The wiring including copper is a wiring including a laminate film of at least a conductive film containing copper as its main component, subjected to microfabricaiton, and the barrier conductive film.
摘要翻译：本发明的目的是抑制由于布线电阻引起的电压降的影响，使显示装置的图像质量均匀。此外，本发明的另一个目的是抑制由于用于将驱动电路部分电连接到输入/输出端子的布线的延迟，以提高驱动电路部分中的操作速度。在本发明中，作为用于半导体器件的布线，使用用于实现降低的布线电阻的铜的布线被用作用于防止铜的扩散的阻挡导电膜，作为布线的一部分包括铜以形成包括铜的布线，而不会将铜扩散到TFT的半导体层中。包括铜的布线是包括至少包含铜作为其主要成分的导电膜，经受微细加工的层压膜和阻挡导电膜的布线。

7. 发明授权

US07510966B2 Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines 有权
标题翻译：导电线，形成导电线的方法以及在多晶硅栅极线上制造钛硅化物时还原钛硅化物聚集的方法
公开(公告)号：US07510966B2
公开(公告)日：2009-03-31
申请号：US11074106
申请日：2005-03-07
申请人： Qi Pan , Jiutao Li , Yongjun Jeff Hu , Allen McTeer
发明人： Qi Pan , Jiutao Li , Yongjun Jeff Hu , Allen McTeer
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/28061 , H01L21/28518 , H01L21/2855 , H01L23/485 , H01L27/10891 , H01L29/4933 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.
摘要翻译：本发明包括导电线，形成导电线的方法，以及在多晶硅晶体管栅极线上制造钛硅化物时还原钛硅化物聚集的方法。在一个实施方案中，形成导电线的方法包括在衬底上提供含硅层。在含硅层之上形成导电层。在该导电层上形成一个含有MSixNy的层，其中“x”为0至3.0，“y”为0.5至10，“M”为Ta，Hf，Mo和W中的至少一种。在包括MSixNy的层上形成包含MSI的层，其中“z”为1至3.0。在包含MSiz的层上形成含TiSia层，其中“a”为1至3.0。将包含硅的层，导电层，含MSixNy的层，包含MSiz的层和含TiSia的层图案化成包括导电线的堆叠。考虑了其他方面和实现。

8. 发明授权

US07492047B2 Semiconductor device and its manufacture method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07492047B2
公开(公告)日：2009-02-17
申请号：US11116424
申请日：2005-04-28
申请人： Narumi Ohkawa
发明人： Narumi Ohkawa
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/14656 , H01L21/7685 , H01L21/76852 , H01L23/53223 , H01L23/53238 , H01L27/14601 , H01L27/14643 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device which comprises a plug layer which is embedded in a window penetrating an inter-layer insulation film, and flattened by using a chemical mechanical polishing, a titanium Ti film which is deposited to extend from the inter-layer insulation film to the plug layer, a titanium nitride TiN film which is deposited on the Ti film, a wiring layer which contains aluminum Al or copper Cu deposited on the TiN film, and an underlying film which is formed between the inter-layer insulation layer and the Ti film.
摘要翻译：半导体器件技术领域本发明涉及一种半导体器件，其包括嵌入在穿透层间绝缘膜的窗口中并通过使用化学机械抛光而变平的插塞层，钛Ti膜从层间隔层绝缘膜到插塞层，沉积在Ti膜上的氮化钛TiN膜，沉积在TiN膜上的包含铝Al或铜Cu的布线层，以及形成在层间绝缘层和Ti膜。

9. 发明申请

US20080099919A1 SEMICONDUCTOR DEVICE INCLUDING COPPER INTERCONNECT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：包括铜互连的半导体器件及其制造方法
公开(公告)号：US20080099919A1
公开(公告)日：2008-05-01
申请号：US11865219
申请日：2007-10-01
申请人： Koichi Ozawa
发明人： Koichi Ozawa
IPC分类号： H01L21/4763 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/76852 , H01L21/76885 , H01L23/5283 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device includes a semiconductor element, a copper interconnect electrically connected to the semiconductor element, a barrier layer containing metal capable of suppressing diffusion and oxidation of copper and continuously covers top and side surfaces of the copper interconnect, and an adhesive layer formed on a top surface of the barrier layer.
摘要翻译：半导体器件包括半导体元件，与半导体元件电连接的铜互连，含有能够抑制铜的扩散和氧化并连续覆盖铜互连的顶表面和侧表面的金属的阻挡层，以及形成在顶部上的粘合层阻挡层的表面。

10. 发明申请

US20070222071A1 Nitrogen Rich Barrier Layers and Methods of Fabrication Thereof 有权
标题翻译：富氮屏障层及其制作方法
公开(公告)号：US20070222071A1
公开(公告)日：2007-09-27
申请号：US11755642
申请日：2007-05-30
申请人： Bum Ki Moon
发明人： Bum Ki Moon
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L2221/1078
摘要： A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.
摘要翻译：半导体器件包括材料层和设置在材料层上的第一阻挡层。第一阻挡层包括形成在第一阻挡层的顶表面处的富氮区域。导体设置在第一阻挡层之上，使得第一阻挡层和富氮区在材料层和导体之间形成阻挡层。

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