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1. 发明授权

US06605513B2 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权
标题翻译：使用一步快速热退火工艺和后端加工形成硅化镍的方法
公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译：自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。去除未反应的镍。然后将电介质层沉积在高电阻镍硅化物区域上。在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

2. 发明授权

US06562718B1 Process for forming fully silicided gates 有权
标题翻译：完全硅化物门的制作工艺
公开(公告)号：US06562718B1
公开(公告)日：2003-05-13
申请号：US09729700
申请日：2000-12-06
申请人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
发明人： Qi Xiang , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , George J. Kluth , Minh V. Ngo , Eric N. Paton , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28097
摘要： A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.
摘要翻译：形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。屏蔽层被覆盖在该器件上。然后露出栅电极的顶表面。沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏。

3. 发明授权

US06372673B1 Silicon-starved nitride spacer deposition 有权
标题翻译：缺硅氮化物间隔物沉积
公开(公告)号：US06372673B1
公开(公告)日：2002-04-16
申请号：US09781256
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21318
CPC分类号： H01L29/665 , H01L21/3185
摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
摘要翻译：通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应，例如镍。

4. 发明授权

US06387767B1 Nitrogen-rich silicon nitride sidewall spacer deposition 失效
标题翻译：富氮氮化硅侧壁间隔物沉积
公开(公告)号：US06387767B1
公开(公告)日：2002-05-14
申请号：US09781448
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.
摘要翻译：使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

5. 发明授权

US06521529B1 HDP treatment for reduced nickel silicide bridging 有权
标题翻译： HDP处理用于还原硅化镍桥接
公开(公告)号：US06521529B1
公开(公告)日：2003-02-18
申请号：US09679880
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Ercan Adem , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Ercan Adem , Robert A. Huertas
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6656 , Y10S257/90
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.
摘要翻译：通过用HDP等离子体处理氮化硅侧壁间隔物的暴露表面以氧化硅化镍，在硅化和除去任何未反应的镍之后，阻止栅电极上的硅化镍层与氮化硅侧壁间隔物的源/漏区之间的桥接其上形成包含硅氧烷氧化物和氮氧化硅的表面层。实施例包括用HDP等离子体处理氮化硅侧壁间隔物以形成厚度为大约至大约的表面氧化硅/氧氮化硅区域。

6. 发明授权

US06724051B1 Nickel silicide process using non-reactive spacer 有权
标题翻译：使用非反应性间隔物的硅化镍工艺
公开(公告)号：US06724051B1
公开(公告)日：2004-04-20
申请号：US09679877
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , Minh Van Ngo , George Jonathan Kluth
发明人： Christy Mei-Chu Woo , Minh Van Ngo , George Jonathan Kluth
IPC分类号： H01L2976
CPC分类号： H01L29/665 , H01L29/4983 , Y10S257/90
摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物，第一和第二侧壁间隔物以及镍硅化物层。栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。栅电极具有第一和第二相对的侧壁，并且第一和第二侧壁间隔件分别设置成与第一和第二侧壁相邻。第一和第二侧壁间隔物由基本上不与镍反应的低K间隔材料形成，例如SiHC，氢倍半硅氧烷和甲基倍半硅氧烷。硅化镍层设置在源/漏区和栅电极上。还公开了制造半导体器件的方法。

7. 发明授权

US06661067B1 Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
标题翻译：氮等离子体处理用于还原硅化镍桥接
公开(公告)号：US06661067B1
公开(公告)日：2003-12-09
申请号：US10260514
申请日：2002-10-01
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

8. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

9. 发明授权

US06507123B1 Nickel silicide process using UDOX to prevent silicide shorting 有权
标题翻译：使用UDOX的硅化镍工艺防止硅化物短路
公开(公告)号：US06507123B1
公开(公告)日：2003-01-14
申请号：US09679878
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
发明人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/6656
摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物。第一和第二组侧壁间隔物和镍硅化物层。栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。栅电极具有第一和第二相对的侧壁，并且第一组侧壁间隔物形成为未掺杂的氧化硅，并且分别设置在第一和第二侧壁附近。第二组侧壁间隔件由氮化硅形成，并且分别设置在第一组侧壁间隔件附近。硅化镍层设置在源/漏区和栅电极上。由未掺杂的氧化硅形成的第二组侧壁间隔件防止在第二组侧壁间隔物上形成硅化镍。还公开了制造半导体器件的方法。

10. 发明授权

US06545370B1 Composite silicon nitride sidewall spacers for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的复合氮化硅侧壁间隔物
公开(公告)号：US06545370B1
公开(公告)日：2003-04-08
申请号：US09679375
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/4983 , H01L29/6656
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.
摘要翻译：通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅层，具有小于约1.95的折射率和约350至约的厚度。

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