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1. 发明授权

US07629202B2 Method and apparatus for electrostatic discharge protection using a temporary conductive coating 失效
标题翻译：使用临时导电涂层进行静电放电保护的方法和装置
公开(公告)号：US07629202B2
公开(公告)日：2009-12-08
申请号：US11532551
申请日：2006-09-18
申请人： Jonas R Weiss , Thomas E. Morf , Heike E Riel
发明人： Jonas R Weiss , Thomas E. Morf , Heike E Riel
IPC分类号： H10L21/44
CPC分类号： H01L23/60 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/11821 , H01L2224/11823 , H01L2224/11825 , H01L2224/11826 , H01L2224/11827 , H01L2224/11831 , H01L2224/1184 , H01L2224/13109 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13171 , H01L2224/13172 , H01L2224/13184 , H01L2224/13187 , H01L2224/13562 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/13601 , H01L2224/13617 , H01L2224/13624 , H01L2224/13644 , H01L2224/13687 , H01L2224/1369 , H01L2224/165 , H01L2224/81002 , H01L2224/81007 , H01L2224/81191 , H01L2224/81411 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30205 , H01L2924/04941 , H01L2924/01003 , H01L2924/0535 , H01L2924/07812
摘要： A method and apparatus for providing ESD protection of an integrated circuit using a temporary conductive coating. The method deposits a temporary conductive coating upon a chip die between contacts to be protected such that a conductive path is created between contacts, provides a carrier substrate that is then bonded to the chip die and then the conductive coating is deactivated to ready the device for use. The deactivation of the conductive coating may involve physical removal of the conductive coating (or a portion thereof), oxidation of the conductive coating to form a non-conductive coating, or some other process to interrupt the conductive path between contacts. The apparatus of the invention is a chip having a temporary conductive coating deposited thereon to protect the integrated circuit from ESD events.
摘要翻译：一种用于使用临时导电涂层提供集成电路的ESD保护的方法和装置。该方法将待保护的触点之间的临时导电涂层沉积在芯片芯片上，使得在触点之间产生导电路径，提供随后结合到芯片模具的载体基板，然后导电涂层停用以准备该装置使用。导电涂层的失活可以涉及导电涂层（或其一部分）的物理去除，导电涂层的氧化以形成非导电涂层，或者一些其它中断接触之间的导电路径的过程。本发明的装置是其上沉积有临时导电涂层的芯片，以保护集成电路免受ESD事件的影响。

2. 发明授权

US07148140B2 Partial plate anneal plate process for deposition of conductive fill material 有权
公开(公告)号：US07148140B2
公开(公告)日：2006-12-12
申请号：US10901857
申请日：2004-07-28
申请人： Montray Leavy , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell
发明人： Montray Leavy , Stephan Grunow , Satyavolu S. Papa Rao , Noel M. Russell
IPC分类号： H10L21/44
CPC分类号： H01L21/76877 , H01L21/76883
摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

3. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

4. 发明授权

US6162659A Method for manufacturing a package structure having a heat spreader for integrated circuit chips 失效
标题翻译：一种用于制造具有用于集成电路芯片的散热器的封装结构的方法
公开(公告)号：US6162659A
公开(公告)日：2000-12-19
申请号：US263033
申请日：1999-03-05
申请人： Leon Li-Heng Wu
发明人： Leon Li-Heng Wu
IPC分类号： H01L23/36 , H01L23/433 , H01L23/498 , H10L21/44
CPC分类号： H01L23/433 , H01L23/36 , H01L23/49816 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/16152 , H01L2224/0401
摘要： A method for manufacturing package structure integrated circuit chips having a heat spreader is disclosed. A wiring substrate is first provided. An integrated circuit chip, having a first surface and a second surface, is then electrically and mechanically connected to the wiring substrate via a first set of solder joints. A heat spreader is subsequently connected to the second surface of the integrated circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on a silicon layer.
摘要翻译：公开了一种制造具有散热器的封装结构集成电路芯片的方法。首先提供布线基板。具有第一表面和第二表面的集成电路芯片然后通过第一组焊接点电连接和机械地连接到布线基板。散热器随后通过第二组焊接点连接到集成电路芯片的第二表面。散热器在硅层上包括粘附促进层。

5. 发明授权

US07186637B2 Method of bonding semiconductor devices 有权
标题翻译：半导体器件接合方法
公开(公告)号：US07186637B2
公开(公告)日：2007-03-06
申请号：US10631508
申请日：2003-07-31
申请人： Grant Kloster , Shriram Ramanathan , Chin-Chang Chen , Paul Fischer
发明人： Grant Kloster , Shriram Ramanathan , Chin-Chang Chen , Paul Fischer
IPC分类号： H10L21/44 , H10L23/52 , H10L23/48 , H10L23/40 , H10L23/485
CPC分类号： H01L21/76251 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/1146 , H01L2224/1148 , H01L2224/11825 , H01L2224/11826 , H01L2224/13022 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13562 , H01L2224/13565 , H01L2224/1357 , H01L2224/13578 , H01L2224/13624 , H01L2224/13657 , H01L2224/13666 , H01L2224/13681 , H01L2224/13684 , H01L2224/13687 , H01L2224/81097 , H01L2224/81193 , H01L2224/81895 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , Y10T29/49128 , Y10T428/24917 , H01L2924/00014
摘要： A method of bonding semiconductor devices is disclosed. The method comprises providing a first substrate having a first conductive interconnecting structure formed thereon and a second substrate having a second conductive interconnecting structure formed thereon. A first conductive passivation layer is selectively formed over exposed areas of the first conductive interconnecting structure. A second conductive passivation layer is selectively formed over exposed areas of the second conductive interconnecting structure. The first substrate and the second substrate are bonded together in such a way that the first conductive passivation layer bonds to the second conductive passivation layer to create a passivation-passivation interface.
摘要翻译：公开了半导体器件的接合方法。该方法包括提供其上形成有第一导电互连结构的第一基板和在其上形成有第二导电互连结构的第二基板。在第一导电互连结构的暴露区域上选择性地形成第一导电钝化层。在第二导电互连结构的暴露区域上有选择地形成第二导电钝化层。第一衬底和第二衬底以这样的方式结合在一起，使得第一导电钝化层结合到第二导电钝化层以产生钝化钝化界面。

6. 发明授权

US07067420B2 Methods for forming a metal layer on a semiconductor 有权
标题翻译：在半导体上形成金属层的方法
公开(公告)号：US07067420B2
公开(公告)日：2006-06-27
申请号：US10404360
申请日：2003-04-01
申请人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
发明人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
IPC分类号： H10L21/4763 , H10L21/20 , H10L21/44
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/45542 , C23C16/45553 , H01L21/28562 , H01L21/32051 , H01L21/76877
摘要： A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
摘要翻译：金属层形成在集成电路器件上，包括在集成电路衬底上形成绝缘层。通过选择性地蚀刻绝缘层从而部分地暴露衬底而形成接触孔。包括氮化钽的金属层使用包括钽元素的钽前体和与钽元素化学键合的至少一个结合元件在包括接触孔的绝缘层上形成。至少一个键合元件的一部分包括与钽元素配位键合的至少一个配体结合元件。形成金属层可以包括用基本上不含氢自由基的去除气体去除至少一些配体键合元件。可以使用化学气相沉积（CVD）或原子层沉积（ALD）工艺来形成金属层。可以在包括氮化钽的金属层上沉积铜或其它金属层。

7. 发明授权

US06946378B2 Methods for fabricating protective structures for bond wires 失效
标题翻译：用于制造接合线的保护结构的方法
公开(公告)号：US06946378B2
公开(公告)日：2005-09-20
申请号：US10396849
申请日：2003-03-25
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： G01R1/04 , H01L21/68 , H10L21/44
CPC分类号： H01L21/6835 , B33Y10/00 , B33Y30/00 , B33Y50/00 , B33Y70/00 , B33Y80/00 , G01R1/0483 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2924/00014 , H01L2924/01039 , H01L2924/1815 , H01L2924/3025 , H01L2224/05599
摘要： A method for fabricating a protective structure for bond wires of a semiconductor device assembly which includes sequentially fabricating one or more layers of the protective structure. After a first layer is formed, each subsequent layer is superimposed upon, contiguous with, and mutually adhered to an underlying layer of the protective structure. Such structure may be used to protect the bond wires of a test apparatus, which connect the contact pads of a carrier substrate of the test apparatus to corresponding bond pads of a test substrate. In addition, a fence member may be assembled with or formed on the test substrate to align and receive a semiconductor device and, thereby, to facilitate assembly of the semiconductor device with the test substrate. The fence member can be formed integrally with the protective structures or secured over the protective structures. Stereolithographic processes may be used to fabricate the fence member.
摘要翻译：一种用于制造半导体器件组件的接合线的保护结构的方法，包括依次制造一层或多层保护结构。在形成第一层之后，每个后续层叠加在保护结构的下层上，与之相邻并相互粘合。这种结构可用于保护将测试装置的载体衬底的接触焊盘连接到测试衬底的相应接合焊盘的测试装置的接合线。此外，栅栏构件可以组装在测试衬底上或形成在测试衬底上以对准和接收半导体器件，从而便于半导体器件与测试衬底的组装。篱笆构件可以与保护结构一体形成或固定在保护结构上。立体光刻工艺可用于制造栅栏构件。

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