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1. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

2. 发明授权

US07241700B1 Methods for post offset spacer clean for improved selective epitaxy silicon growth 有权
标题翻译：用于后置偏移间隔物清洁的方法用于改善选择性外延硅生长
公开(公告)号：US07241700B1
公开(公告)日：2007-07-10
申请号：US10969769
申请日：2004-10-20
申请人： William George En , Eric N. Paton , Scott D. Luning
发明人： William George En , Eric N. Paton , Scott D. Luning
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0206 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/30608 , H01L21/823864 , H01L29/66636
摘要： A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.
摘要翻译：栅极结构形成在衬底上。衬底的源极/漏极区域暴露于包含氢氧化铵，过氧化氢和去离子水的溶液中，以蚀刻源极/漏极区域的最上半个半导体端口。

3. 发明授权

US07091097B1 End-of-range defect minimization in semiconductor device 有权
标题翻译：半导体器件的范围内缺陷最小化
公开(公告)号：US07091097B1
公开(公告)日：2006-08-15
申请号：US10933424
申请日：2004-09-03
申请人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
发明人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

4. 发明授权

US06811448B1 Pre-cleaning for silicidation in an SMOS process 有权
标题翻译：在SMOS工艺中预硅化硅化
公开(公告)号：US06811448B1
公开(公告)日：2004-11-02
申请号：US10619879
申请日：2003-07-15
申请人： Eric N. Paton , Paul R. Besser , Qi Xiang
发明人： Eric N. Paton , Paul R. Besser , Qi Xiang
IPC分类号： H01L21302
CPC分类号： H01L21/02054 , H01L21/02046 , H01L21/02052 , H01L21/28518 , H01L29/665
摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用用于从晶片顶表面去除自然氧化物的协议。暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。该方案可以使用氟化氢浸渍。在使用等离子体之前可以使用氟化氢浸渍。该协议允许在SMOS器件中更好的硅化。

5. 发明授权

US06764912B1 Passivation of nitride spacer 有权
标题翻译：氮化物间隔物钝化
公开(公告)号：US06764912B1
公开(公告)日：2004-07-20
申请号：US09919943
申请日：2001-08-02
申请人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
发明人： John Clayton Foster , Eric N. Paton , Matthew S. Buynoski , Qi Xiang , Paul R. Besser , Paul L. King
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656
摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.
摘要翻译：栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

6. 发明授权

US06743689B1 Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions 失效
标题翻译：制造具有精确定义的单晶源极/漏极延伸的SOI器件的方法
公开(公告)号：US06743689B1
公开(公告)日：2004-06-01
申请号：US10341427
申请日：2003-01-14
申请人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
发明人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/268 , H01L29/458 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.
摘要翻译：包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造源/漏扩展的结晶和激活。实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分。

7. 发明授权

US06703277B1 Reducing agent for high-K gate dielectric parasitic interfacial layer 有权
标题翻译：用于高K栅介质寄生界面层的还原剂
公开(公告)号：US06703277B1
公开(公告)日：2004-03-09
申请号：US10118437
申请日：2002-04-08
申请人： Eric N. Paton , Bin Yu
发明人： Eric N. Paton , Bin Yu
IPC分类号： H01L218242
CPC分类号： H01L21/31691 , H01L21/28176 , H01L21/28194 , H01L21/28291 , H01L21/3115 , H01L21/31155 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/78
摘要： A semiconductor device and a process for fabricating the device, the process including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide. In another embodiment, the metal is implanted into the interfacial layer. A semiconductor device including such metal layer and implanted metal is also provided.
摘要翻译：一种半导体器件和用于制造该器件的工艺，该工艺包括以下步骤：在硅衬底上沉积包含至少一种高K电介质材料的层，由此在硅衬底与硅衬底之间的界面处形成一定数量的二氧化硅高K介电材料层; 在高K电介质材料层上沉积一层金属; 并且通过高K电介质材料层使金属扩散，由此金属将至少一部分二氧化硅还原为硅，并且金属被氧化以形成K值大于二氧化硅的电介质材料。在另一个实施方案中，将金属注入界面层。还提供了包括这种金属层和植入金属的半导体器件。

8. 发明授权

US06646307B1 MOSFET having a double gate 有权
标题翻译：具有双栅极的MOSFET
公开(公告)号：US06646307B1
公开(公告)日：2003-11-11
申请号：US10081362
申请日：2002-02-21
申请人： Bin Yu , Eric N. Paton
发明人： Bin Yu , Eric N. Paton
IPC分类号： H01L2701
CPC分类号： H01L29/6675 , H01L29/78618 , H01L29/78648
摘要： A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.
摘要翻译：双栅极MOSFET。 MOSFET包括设置在底栅电极上的底栅电极和底栅电介质。半导体本体区域设置在底栅电介质和底栅电极之上，并且设置在源极和漏极之间。顶栅电极设置在身体上。顶栅电介质分离顶栅电极和主体，顶栅电极和底栅电极在主体内限定通道并置于源极和漏极之间。底栅电介质或顶栅电介质中的至少一个由高K材料形成。还公开了一种形成双栅极MOSFET的方法，其中用于形成本体的半导体膜使用半导体衬底作为晶种再结晶。

9. 发明授权

US06605513B2 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权
标题翻译：使用一步快速热退火工艺和后端加工形成硅化镍的方法
公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译：自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。去除未反应的镍。然后将电介质层沉积在高电阻镍硅化物区域上。在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

10. 发明授权

US06602781B1 Metal silicide gate transistors 有权
标题翻译：金属硅化物晶体管
公开(公告)号：US06602781B1
公开(公告)日：2003-08-05
申请号：US09734207
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2144
CPC分类号： H01L21/28202 , H01L21/28097 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/66606 , H01L29/7833
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了金属在凹部中的部分之外，除去金属。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

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