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1. 发明申请

US20130043589A1 Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device 审中-公开
标题翻译：在半导体器件上形成导线上的非平面盖层的方法
公开(公告)号：US20130043589A1
公开(公告)日：2013-02-21
申请号：US13210858
申请日：2011-08-16
申请人： Ryoung-Han Kim , Errol Todd Ryan
发明人： Ryoung-Han Kim , Errol Todd Ryan
IPC分类号： H01L23/532 , H01L21/768 , H01L23/50
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material. In another example, the device includes a conductive structure positioned in a layer of insulating material and a first cap layer formed on the layer of insulating material and the conductive structure, wherein a first interface between the first cap layer and the layer of insulating material is located in a first plane and a second interface between the first cap layer and the conductive structure is located in a second plane that is different from the first plane.
摘要翻译：这里公开了形成在半导体器件上的导电线之上形成非平面覆盖层的方法的各种方法，以及结合有这种非平面覆盖层的器件。在一个说明性示例中，该方法包括在绝缘材料层中形成导电结构，使导电结构的上表面相对于绝缘材料层的上表面凹陷，使得导电结构的凹陷的上表面和绝缘材料层的上表面位于不同的平面中，并且在凹陷导电结构的上表面之后，在导电结构和绝缘材料层上形成第一盖层。在另一示例中，该器件包括位于绝缘材料层中的导电结构和形成在绝缘材料层和导电结构上的第一覆盖层，其中第一覆盖层和绝缘材料层之间的第一界面是位于第一平面中，并且第一盖层和导电结构之间的第二界面位于与第一平面不同的第二平面中。

2. 发明授权

US06969678B1 Multi-silicide in integrated circuit technology 失效
标题翻译：集成电路技术中的多硅化物
公开(公告)号：US06969678B1
公开(公告)日：2005-11-29
申请号：US10700711
申请日：2003-11-03
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供一种形成集成电路的方法和集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

3. 发明授权

US06809032B1 Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques 有权
标题翻译：使用光学技术检测化学机械抛光操作的终点的方法和装置
公开(公告)号：US06809032B1
公开(公告)日：2004-10-26
申请号：US10136513
申请日：2002-05-01
申请人： Frank Mauersberger , Peter J. Beckage , Paul R. Besser , Frederick N. Hause , Errol Todd Ryan , William S. Brennan , John A. Iacoponi
发明人： Frank Mauersberger , Peter J. Beckage , Paul R. Besser , Frederick N. Hause , Errol Todd Ryan , William S. Brennan , John A. Iacoponi
IPC分类号： H01L21302
CPC分类号： B24B37/013 , B24B49/12 , H01L21/3212 , H01L21/76801 , H01L21/7684 , H01L21/76877
摘要： In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device. The controller is capable of determining the second material, instructing the controllable light source to deliver light of one of the frequencies in response to the second material, comparing the reflected light to a preselected setpoint, and modifying the polishing process in response to the reflected light exceeding the preselected setpoint.
摘要翻译：在本发明的另一方面，提供了一种用于在抛光过程中检测端点的系统。该系统包括抛光工具，可控光源，传感器和控制器。抛光工具能够抛光半导体器件的表面，其中半导体器件包括由第一材料构成的第一层和由第二材料构成的第二层。第一层位于第二层之上。可控光源能够将具有多个预选频率中的一个的光传送到半导体器件的表面。传感器能够检测从半导体器件的表面反射的光。所述控制器能够确定所述第二材料，指示所述可控光源响应于所述第二材料传送所述频率之一的光，将所述反射光与预选设定值进行比较，以及响应于所述反射光修改所述抛光过程超过预选设定值。

4. 发明授权

US06413846B1 Contact each methodology and integration scheme 有权
标题翻译：接触蚀刻方法和集成方案
公开(公告)号：US06413846B1
公开(公告)日：2002-07-02
申请号：US09712501
申请日：2000-11-14
申请人： Paul R. Besser , Errol Todd Ryan , Frederick N. Hause , Frank Mauersberger , William S. Brennan , John A. Iacoponi , Peter J. Beckage
发明人： Paul R. Besser , Errol Todd Ryan , Frederick N. Hause , Frank Mauersberger , William S. Brennan , John A. Iacoponi , Peter J. Beckage
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/76802 , Y10S438/97
摘要： A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.
摘要翻译：本文公开了一种形成导电触头或集成电路器件的方法。在一个实施例中，该方法包括在半导体衬底上形成晶体管，以及在晶体管和衬底之上形成由原硅酸盐玻璃材料组成的第一层。该方法还包括在第一层之上形成由绝缘材料构成的第二层，并且执行至少一个蚀刻工艺以在第二层中限定用于要在其中形成的导电接触的开口，其中，由原硅酸盐玻璃材料在蚀刻第二层中的开口期间用作蚀刻停止层。

5. 发明授权

US07670915B1 Contact liner in integrated circuit technology 有权
标题翻译：接触式衬板集成电路技术
公开(公告)号：US07670915B1
公开(公告)日：2010-03-02
申请号：US10791096
申请日：2004-03-01
申请人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
发明人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
IPC分类号： H01L21/20
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成硅化物。在半导体衬底的上方形成有具有接触孔的层间电介质。接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

6. 发明授权

US06967158B2 Method for forming a low-k dielectric structure on a substrate 有权
标题翻译：在衬底上形成低k电介质结构的方法
公开(公告)号：US06967158B2
公开(公告)日：2005-11-22
申请号：US10384398
申请日：2003-03-07
申请人： Yuri Solomentsev , Matthew S. Angyal , Errol Todd Ryan , Susan Gee-Young Kim
发明人： Yuri Solomentsev , Matthew S. Angyal , Errol Todd Ryan , Susan Gee-Young Kim
IPC分类号： H01L21/321 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/3212 , H01L21/76829 , H01L21/7684
摘要： The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.
摘要翻译：本发明提供了一种用于在衬底10上形成低k电介质结构的方法，该方法包括在衬底上沉积介电层12.多层覆盖层18沉积在电介质层上。多层膜层包括第一和第二膜182，其中第二膜设置在电介质层和第一膜之间。第一膜通常具有与其相关联的去除速率小于与第二膜相关联的去除速率。沉积层20沉积在多膜覆盖层上并随后除去。选择多层盖层的性质，以防止在去除沉积膜期间电介质层被曝光/去除。以这种方式，可以平坦化具有可变迁移速率（例如铜）的沉积层，而不会损坏下面的介电层。

7. 发明授权

US08349731B2 Methods for forming copper diffusion barriers for semiconductor interconnect structures 有权
标题翻译：用于形成半导体互连结构的铜扩散阻挡层的方法
公开(公告)号：US08349731B2
公开(公告)日：2013-01-08
申请号：US13072502
申请日：2011-03-25
申请人： Errol Todd Ryan
发明人： Errol Todd Ryan
IPC分类号： H01L21/44
CPC分类号： H01L21/76867 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.
摘要翻译：提供了用于形成用于半导体互连结构的Cu扩散阻挡层的方法的实施例。该方法包括氧化沿着电介质基板设置的铜线的暴露的外部部分以形成氧化铜层。氧化还原金属沉积在氧化铜层上。铜氧化物层被氧化还原金属的至少一部分还原，氧化还原金属氧化形成金属氧化物阻挡层。电介质帽沉积在金属氧化物阻挡层上。

8. 发明授权

US06869879B1 Method for forming conductive interconnects 有权
标题翻译：形成导电互连的方法
公开(公告)号：US06869879B1
公开(公告)日：2005-03-22
申请号：US09706043
申请日：2000-11-03
申请人： Errol Todd Ryan
发明人： Errol Todd Ryan
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76811 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/7681 , H01L21/76813 , H01L21/76838
摘要： A method is provided for forming a conductive interconnect in a semiconductor device. The method comprises forming a dielectric layer above a structure layer, forming a cap layer above the dielectric layer, forming a photoresist layer above the cap layer, and forming an opening in the photoresist layer. A first anisotropic etch is performed into a region of the cap layer underlying the opening in the photoresist layer to form an etched region in the cap layer, leaving a portion of the cap layer in the etched region. The pattern in the photoresist is transferred into the cap layer. The photoresist layer is removed from above the cap layer while the remaining portion of the cap layer in the etched region protects the dielectric layer from damage by the photoresist removal process. A second anisotropic etch is performed to form an opening in the dielectric layer, the opening in the dielectric layer having a sidewall. A barrier layer is formed above at least the sidewall of the opening in the dielectric layer, and a conductive material is deposited to fill at least the opening in the dielectric layer.
摘要翻译：提供了一种用于在半导体器件中形成导电互连的方法。该方法包括在结构层之上形成电介质层，在电介质层之上形成覆盖层，在覆盖层上方形成光致抗蚀剂层，并在光刻胶层中形成开口。在光致抗蚀剂层中的开口下面的盖层的区域中进行第一各向异性蚀刻，以在盖层中形成蚀刻区域，在蚀刻区域中留下盖层的一部分。光致抗蚀剂中的图案被转移到盖层中。光刻胶层从盖层上方被去除，而蚀刻区域中的盖层的剩余部分保护介电层免受光致抗蚀剂去除过程的损害。执行第二各向异性蚀刻以在电介质层中形成开口，电介质层中的开口具有侧壁。至少在电介质层中的开口的侧壁上形成阻挡层，并且沉积导电材料以至少填充介电层中的开口。

9. 发明授权

US06514858B1 Test structure for providing depth of polish feedback 失效
标题翻译：提供抛光反馈深度的测试结构
公开(公告)号：US06514858B1
公开(公告)日：2003-02-04
申请号：US09829202
申请日：2001-04-09
申请人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
发明人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
IPC分类号： H01L214763
CPC分类号： H01L22/34 , B24B37/042 , B24B49/00 , H01L21/31053 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.
摘要翻译：提供了一种用于控制半导体器件的抛光工艺的测试结构。测试结构由结构层，第一处理层和互连构成。第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

10. 发明申请

US20120244698A1 METHODS FOR FORMING COPPER DIFFUSION BARRIERS FOR SEMICONDUCTOR INTERCONNECT STRUCTURES 有权
标题翻译：形成用于半导体互连结构的铜扩散障碍的方法
公开(公告)号：US20120244698A1
公开(公告)日：2012-09-27
申请号：US13072502
申请日：2011-03-25
申请人： Errol Todd RYAN
发明人： Errol Todd RYAN
IPC分类号： H01L21/768
CPC分类号： H01L21/76867 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.
摘要翻译：提供了用于形成用于半导体互连结构的Cu扩散阻挡层的方法的实施例。该方法包括氧化沿着电介质基板设置的铜线的暴露的外部部分以形成氧化铜层。氧化还原金属沉积在氧化铜层上。铜氧化物层被氧化还原金属的至少一部分还原，氧化还原金属氧化形成金属氧化物阻挡层。电介质帽沉积在金属氧化物阻挡层上。

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