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1. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

2. 发明授权

US07670915B1 Contact liner in integrated circuit technology 有权
标题翻译：接触式衬板集成电路技术
公开(公告)号：US07670915B1
公开(公告)日：2010-03-02
申请号：US10791096
申请日：2004-03-01
申请人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
发明人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
IPC分类号： H01L21/20
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成硅化物。在半导体衬底的上方形成有具有接触孔的层间电介质。接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

3. 发明授权

US07151020B1 Conversion of transition metal to silicide through back end processing in integrated circuit technology 有权
标题翻译：在集成电路技术中通过后端处理将过渡金属转化为硅化物
公开(公告)号：US07151020B1
公开(公告)日：2006-12-19
申请号：US10839437
申请日：2004-05-04
申请人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
发明人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成过渡金属层。在半导体衬底上形成层间电介质。然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。

4. 发明授权

US06969678B1 Multi-silicide in integrated circuit technology 失效
标题翻译：集成电路技术中的多硅化物
公开(公告)号：US06969678B1
公开(公告)日：2005-11-29
申请号：US10700711
申请日：2003-11-03
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供一种形成集成电路的方法和集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

5. 发明授权

US07843015B2 Multi-silicide system in integrated circuit technology 有权
标题翻译：集成电路技术中的多硅化物系统
公开(公告)号：US07843015B2
公开(公告)日：2010-11-30
申请号：US11229188
申请日：2005-09-15
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/02
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

6. 发明授权

US07049666B1 Low power pre-silicide process in integrated circuit technology 有权
标题翻译：集成电路技术中的低功耗预硅化工艺
公开(公告)号：US07049666B1
公开(公告)日：2006-05-23
申请号：US10859286
申请日：2004-06-01
申请人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
发明人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L29/94 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成一个薄的绝缘层。在薄绝缘层和栅极上形成硅化物。在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

7. 发明授权

US07307322B2 Ultra-uniform silicide system in integrated circuit technology 有权
标题翻译：集成电路技术中超均匀的硅化物系统
公开(公告)号：US07307322B2
公开(公告)日：2007-12-11
申请号：US11252493
申请日：2005-10-17
申请人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
发明人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L29/76
CPC分类号： H01L21/28518
摘要： A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
摘要翻译：提供集成电路的结构。在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。然后在介电层中形成与超均匀硅化物的接触。

8. 发明授权

US07005376B2 Ultra-uniform silicides in integrated circuit technology 有权
标题翻译：集成电路技术中超均匀的硅化物
公开(公告)号：US07005376B2
公开(公告)日：2006-02-28
申请号：US10615086
申请日：2003-07-07
申请人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
发明人： Robert J. Chiu , Jeffrey P. Patton , Paul R. Besser , Minh Van Ngo
IPC分类号： H01L21/00
CPC分类号： H01L21/28518
摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
摘要翻译：提供一种集成电路的形成方法和结构。在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。然后在电介质层中形成与超均匀硅化物的接触。

9. 发明申请

US20090050471A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS 审中-公开
标题翻译：形成电子器件的方法，包括开孔中的沉积层
公开(公告)号：US20090050471A1
公开(公告)日：2009-02-26
申请号：US11844518
申请日：2007-08-24
申请人： Robert J. Chiu , Connie Pin-Chin Wang , Minh Van Ngo , Simon S. Chan
发明人： Robert J. Chiu , Connie Pin-Chin Wang , Minh Van Ngo , Simon S. Chan
IPC分类号： C23C14/32
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76814 , H01L23/485
摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.
摘要翻译：形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。

10. 发明授权

US06576548B1 Method of manufacturing a semiconductor device with reliable contacts/vias 有权
标题翻译：制造具有可靠接触/通孔的半导体器件的方法
公开(公告)号：US06576548B1
公开(公告)日：2003-06-10
申请号：US10079861
申请日：2002-02-22
申请人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
发明人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/31105 , H01L21/76804 , H01L21/76846 , H01L21/76877
摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.
摘要翻译：通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层，在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨约1,900至约2,300埃/分钟以填充开口。

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