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1. 发明授权

US07249010B1 Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA 有权
标题翻译：估计在FPGA中实现的设计对单事件不匹配的敏感性的方法
公开(公告)号：US07249010B1
公开(公告)日：2007-07-24
申请号：US10407280
申请日：2003-04-03
申请人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
发明人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F13/00 , G06F17/50 , G06F9/00 , G01R31/08 , G01F19/00 , G06F11/34 , G06F15/00 , G21C17/00 , H03K17/693 , H03K17/687
CPC分类号： G06F17/5054 , G06F2217/70
摘要： Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.
摘要翻译：估计在FPGA中实现的设计对单事件扰乱（SEU）的敏感性的方法。在FPGA中，许多配置存储单元可以响应于SEU而改变状态，而不影响在FPGA中实现的设计的功能。根据本发明的方法，确定“关心位”（与设计中实际使用的资源相关联的位）的数量。保留位的数量占FPGA中配置存储单元总数的比例决定了“SEU概率影响”（SEUPI）值。 “平均平均故障间隔时间”（MTBU）值是在FPGA中的一个配置存储器单元受SEU影响之前平均估计经过多少时间。为了获得FPGA中设计的“平均故障间隔时间”，MTBU值除以SEUPI值。

2. 发明授权

US07620883B1 Techniques for mitigating, detecting, and correcting single event upset effects 有权
标题翻译：减轻，检测和纠正单事件不安效应的技术
公开(公告)号：US07620883B1
公开(公告)日：2009-11-17
申请号：US11388897
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

3. 发明授权

US06308311B1 Method for reconfiguring a field programmable gate array from a host 有权
标题翻译：从主机重新配置现场可编程门阵列的方法
公开(公告)号：US06308311B1
公开(公告)日：2001-10-23
申请号：US09311627
申请日：1999-05-14
申请人： Carl H. Carmichael , Conrad A. Theron , Donald H. St. Pierre, Jr.
发明人： Carl H. Carmichael , Conrad A. Theron , Donald H. St. Pierre, Jr.
IPC分类号： G06F1750
CPC分类号： G06F15/7867 , G05B2219/21109 , G05B2219/25257 , G06F17/5054
摘要： A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.
摘要翻译：公开了一种用于重新配置接口设备的板上FPGA而不重置接口设备的方法。 FPGA接口设备还包括微控制器，并且板上FPGA具有耦合到第一非易失性存储器的串行数据端口和耦合到第二存储器的并行数据端口，第二存储器可以是易失性存储器。默认配置设计存储在非易失性存储器中。板上FPGA最初处于串行配置模式，因此在上电时，板载FPGA通过其串行端口查看第一个内存，进行配置设计。在需要重新配置板载FPGA的情况下，新的配置设计存储在第二个存储器中，并且板载FPGA被指示以并行模式重新配置。作为响应，机载FPGA通过其并行端口查看第二个存储器，检索新的配置设计，然后相应地重新配置。

4. 发明授权

US07383479B1 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07383479B1
公开(公告)日：2008-06-03
申请号：US11389349
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

5. 发明授权

US06425077B1 System and method for reading data from a programmable logic device 有权
标题翻译：用于从可编程逻辑器件读取数据的系统和方法
公开(公告)号：US06425077B1
公开(公告)日：2002-07-23
申请号：US09312024
申请日：1999-05-14
申请人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
发明人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
IPC分类号： G06F300
CPC分类号： G01R31/31919 , G01R31/318516
摘要： A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.
摘要翻译：一种用于从可编程逻辑器件（PLD）读回数据的系统和方法。构成具有一个或多个时钟偏移值的时钟偏移表。每个时钟偏移值表示从设备读取的所选位被保存并发送到主机的相对时钟周期。从PLD读取数据，每个读回时钟周期以一位的速率读取数据，并且从器件读取位读取回读时钟周期。当回读时钟周期的计数等于偏移量时，该位被选择并保存。

6. 发明授权

US07990173B1 Single event upset mitigation 有权
标题翻译：单次事件不安缓解
公开(公告)号：US07990173B1
公开(公告)日：2011-08-02
申请号：US12725324
申请日：2010-03-16
申请人： Chen W. Tseng , Carl H. Carmichael
发明人： Chen W. Tseng , Carl H. Carmichael
IPC分类号： H03K19/003 , H03K19/007
CPC分类号： H03K19/0033 , H03K19/17764
摘要： A circuit for handling single event upsets includes a plurality of digital clock manager circuits. A plurality of counters are respectively coupled by their inputs to the outputs of the digital clock managers and a reset controller is coupled to the outputs of the counters. The reset controller is configured to determine an expected value of the counters. In response to an output value of one of the counters being less than the expected value, the reset controller triggers a reset of the digital clock manager coupled to the input of the one of the counters. In response to an output value of one of the counters being greater than or equal to the expected value, the reset controller continues operation without triggering a reset of a digital clock manager.
摘要翻译：用于处理单事件故障的电路包括多个数字时钟管理器电路。多个计数器分别通过它们的输入耦合到数字时钟管理器的输出，并且复位控制器耦合到计数器的输出端。复位控制器被配置为确定计数器的期望值。响应于其中一个计数器的输出值小于期望值，复位控制器触发耦合到一个计数器的输入端的数字时钟管理器的复位。响应于其中一个计数器的输出值大于或等于预期值，复位控制器继续操作而不触发数字时钟管理器的复位。

7. 发明授权

US06560665B1 Embedding firmware for a microprocessor with configuration data for a field programmable gate array 有权
标题翻译：为具有现场可编程门阵列配置数据的微处理器嵌入固件
公开(公告)号：US06560665B1
公开(公告)日：2003-05-06
申请号：US09312282
申请日：1999-05-14
申请人： Edwin W. Resler , Conrad A. Theron , Donald H. St. Pierre, Jr. , Carl H. Carmichael
发明人： Edwin W. Resler , Conrad A. Theron , Donald H. St. Pierre, Jr. , Carl H. Carmichael
IPC分类号： G06F1314
CPC分类号： G06F15/7814 , G05B2219/21109
摘要： An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code. Since both the on-board FPGA configuration design and the microcontroller firmware code are stored in a single memory, the dedicated parallel memory previously used to store the microcontroller firmware code may be eliminated, thereby advantageously conserving printed circuit board area.
摘要翻译： FPGA接口设备包括具有并行端口的微控制器，具有输出端口的串行存储器和板载FPGA，其具有耦合到串行PROM的输出端口的串行端口，并且具有耦合到并行端口的并行端口微控制器。 FPGA接口设备板载FPGA的配置设计和接口设备微控制器的固件代码存储在串行存储器中。上电时，板载FPGA从串行存储器读取配置设计，然后相应地进行配置。正确配置后，板载FPGA从串行存储器中串行读取单片机固件代码，并将固件代码并行化，此后可使微控制器访问所产生的并行固件代码。由于车载FPGA配置设计和微控制器固件代码均存储在单个存储器中，所以先前用于存储微控制器固件代码的专用并行存储器可以被消除，从而有利地节省了印刷电路板面积。

8. 发明授权

US07626415B1 Method and apparatus for configuring an integrated circuit 有权
标题翻译：用于配置集成电路的方法和装置
公开(公告)号：US07626415B1
公开(公告)日：2009-12-01
申请号：US12038768
申请日：2008-02-27
申请人： Chen Wei Tseng , Carl H. Carmichael , Gregory J. Miller
发明人： Chen Wei Tseng , Carl H. Carmichael , Gregory J. Miller
IPC分类号： H03K19/003
CPC分类号： H03K19/173 , G11C11/4125 , H03K19/0033
摘要： A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising a configuration storage device containing configuration data, and an integrated circuit, coupled to the configuration storage device, where the integrated circuit comprising at least one configuration management controller for managing a configuration of the integrated circuit in accordance with the configuration data, where the integrated circuit is deployed in a radiation tolerant device.
摘要翻译：公开了一种配置管理系统。例如，本发明的一个实施例提供了一种配置管理系统，其包括配置存储设备，其包含配置数据，以及集成电路，其耦合到配置存储设备，其中该集成电路包括用于管理配置的至少一个配置管理控制器的集成电路根据配置数据，其中集成电路部署在耐辐射装置中。

9. 发明授权

US07576557B1 Method and apparatus for mitigating one or more event upsets 有权
标题翻译：减轻一个或多个事件扰乱的方法和装置
公开(公告)号：US07576557B1
公开(公告)日：2009-08-18
申请号：US12056207
申请日：2008-03-26
申请人： Chen Wei Tseng , Carl H. Carmichael
发明人： Chen Wei Tseng , Carl H. Carmichael
IPC分类号： H03K19/003
CPC分类号： H03K19/17752 , H03K19/17756 , H03K19/17764
摘要： A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable logic of the integrated circuit with a first configuration portion of the configuration bitstream of the memory, monitoring the integrated circuit for at least one configuration error generated in response to an event upset, reconfiguring at least a portion of the programmable logic of the integrated circuit with a second configuration portion of the configuration bitstream in response to the at least one configuration error generated. The integrated circuit may operate normally during the process of reconfiguring the at least a portion of the programmable logic.
摘要翻译：一种配置具有可编程逻辑的集成电路的方法，包括以下步骤：根据配置设置产生配置比特流，将配置比特流存储到存储器的一部分中，用集成电路的可编程逻辑配置第一配置部分所述存储器的配置比特流，响应于事件不正常而产生的至少一个配置错误来监测所述集成电路，响应于所述配置比特流的第二配置部分，重新配置所述集成电路的可编程逻辑的至少一部分产生至少一个配置错误。在重新配置可编程逻辑的至少一部分的过程中，集成电路可以正常运行。

10. 发明授权

US07310759B1 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07310759B1
公开(公告)日：2007-12-18
申请号：US11388728
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G01R31/28 , H03K17/693
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

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