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1. 发明授权

US06560665B1 Embedding firmware for a microprocessor with configuration data for a field programmable gate array 有权
标题翻译：为具有现场可编程门阵列配置数据的微处理器嵌入固件
公开(公告)号：US06560665B1
公开(公告)日：2003-05-06
申请号：US09312282
申请日：1999-05-14
申请人： Edwin W. Resler , Conrad A. Theron , Donald H. St. Pierre, Jr. , Carl H. Carmichael
发明人： Edwin W. Resler , Conrad A. Theron , Donald H. St. Pierre, Jr. , Carl H. Carmichael
IPC分类号： G06F1314
CPC分类号： G06F15/7814 , G05B2219/21109
摘要： An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code. Since both the on-board FPGA configuration design and the microcontroller firmware code are stored in a single memory, the dedicated parallel memory previously used to store the microcontroller firmware code may be eliminated, thereby advantageously conserving printed circuit board area.
摘要翻译： FPGA接口设备包括具有并行端口的微控制器，具有输出端口的串行存储器和板载FPGA，其具有耦合到串行PROM的输出端口的串行端口，并且具有耦合到并行端口的并行端口微控制器。 FPGA接口设备板载FPGA的配置设计和接口设备微控制器的固件代码存储在串行存储器中。上电时，板载FPGA从串行存储器读取配置设计，然后相应地进行配置。正确配置后，板载FPGA从串行存储器中串行读取单片机固件代码，并将固件代码并行化，此后可使微控制器访问所产生的并行固件代码。由于车载FPGA配置设计和微控制器固件代码均存储在单个存储器中，所以先前用于存储微控制器固件代码的专用并行存储器可以被消除，从而有利地节省了印刷电路板面积。

2. 发明授权

US06175530B1 Method for detecting low power on an FPGA interface device 有权
标题翻译：在FPGA接口设备上检测低功耗的方法
公开(公告)号：US06175530B1
公开(公告)日：2001-01-16
申请号：US09312001
申请日：1999-05-14
申请人： Conrad A. Theron , Edwin W. Resler , Donald H. St. Pierre, Jr.
发明人： Conrad A. Theron , Edwin W. Resler , Donald H. St. Pierre, Jr.
IPC分类号： G11C700
CPC分类号： G06F15/7867 , G06F1/30
摘要： A method is disclosed for alerting a user of a low power condition on, for instance, an FPGA interface device. An interface device having a microcontroller and an associated power plane for powering the microcontroller and other component on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system of the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system. In response thereto, the host system may take suitable action such as, for instance, alerting the user, resetting the microcontroller, aborting a download process, and so on.
摘要翻译：公开了一种用于在例如FPGA接口设备上提醒低功率状况的用户的方法。具有微控制器和用于为微控制器和接口装置上的其他部件供电的相关电源平面的接口装置包括耦合以监测相关电力平面的电压电平的检测电路。当电压平面的电压电平下降到预定阈值电压以下时，检测电路向主机系统发送低功率标志。优选地，使用USB端口连接发送到主机系统的低功率标志在接口设备上向主机系统报告低功率状况。选择预定阈值电压为比微控制器的最小工作电压高的适当量，以便允许微控制器有足够的时间将低功率标志发送到主机系统。作为响应，主机系统可以采取适当的动作，例如，提醒用户，重置微控制器，中止下载过程等等。

3. 发明授权

US06425077B1 System and method for reading data from a programmable logic device 有权
标题翻译：用于从可编程逻辑器件读取数据的系统和方法
公开(公告)号：US06425077B1
公开(公告)日：2002-07-23
申请号：US09312024
申请日：1999-05-14
申请人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
发明人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
IPC分类号： G06F300
CPC分类号： G01R31/31919 , G01R31/318516
摘要： A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.
摘要翻译：一种用于从可编程逻辑器件（PLD）读回数据的系统和方法。构成具有一个或多个时钟偏移值的时钟偏移表。每个时钟偏移值表示从设备读取的所选位被保存并发送到主机的相对时钟周期。从PLD读取数据，每个读回时钟周期以一位的速率读取数据，并且从器件读取位读取回读时钟周期。当回读时钟周期的计数等于偏移量时，该位被选择并保存。

4. 发明授权

US06308311B1 Method for reconfiguring a field programmable gate array from a host 有权
标题翻译：从主机重新配置现场可编程门阵列的方法
公开(公告)号：US06308311B1
公开(公告)日：2001-10-23
申请号：US09311627
申请日：1999-05-14
申请人： Carl H. Carmichael , Conrad A. Theron , Donald H. St. Pierre, Jr.
发明人： Carl H. Carmichael , Conrad A. Theron , Donald H. St. Pierre, Jr.
IPC分类号： G06F1750
CPC分类号： G06F15/7867 , G05B2219/21109 , G05B2219/25257 , G06F17/5054
摘要： A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.
摘要翻译：公开了一种用于重新配置接口设备的板上FPGA而不重置接口设备的方法。 FPGA接口设备还包括微控制器，并且板上FPGA具有耦合到第一非易失性存储器的串行数据端口和耦合到第二存储器的并行数据端口，第二存储器可以是易失性存储器。默认配置设计存储在非易失性存储器中。板上FPGA最初处于串行配置模式，因此在上电时，板载FPGA通过其串行端口查看第一个内存，进行配置设计。在需要重新配置板载FPGA的情况下，新的配置设计存储在第二个存储器中，并且板载FPGA被指示以并行模式重新配置。作为响应，机载FPGA通过其并行端口查看第二个存储器，检索新的配置设计，然后相应地重新配置。

5. 发明授权

US6094063A Method for level shifting logic signal voltage levels 有权
标题翻译：电平转换逻辑信号电压电平的方法
公开(公告)号：US6094063A
公开(公告)日：2000-07-25
申请号：US312023
申请日：1999-05-14
申请人： Donald H. St. Pierre, Jr. , Conrad A. Theron
发明人： Donald H. St. Pierre, Jr. , Conrad A. Theron
IPC分类号： H03K19/0185 , H03K19/173
CPC分类号： H03K19/018585
摘要： The present invention provides an apparatus for converting logic signals of a first voltage level to logic signals of a second voltage level in response to a control signal indicative of whether logic signals on an associated target device are of the first or second voltage level. An output configuration includes a de-multiplexer having an input terminal coupled to receive an output signal of an associated logic circuit, a control terminal coupled to receive a control signal, and first and second output terminals, the first de-multiplexer output terminal being connected to the target device. A switch coupled between the second de-multiplexer output terminal and the target device has a control terminal coupled to receive the control signal. When the control signal is in a first state, a voltage drop across the switch converts the logic signals of the first voltage level to logic signals of the second voltage level. When the control signal is in a second state, the switch is not conductive, and the logic signals of the associated logic circuit are provided directly to the target device.
摘要翻译：本发明提供了一种用于响应于指示相关联的目标装置上的逻辑信号是第一或第二电压电平的控制信号，将第一电压电平的逻辑信号转换为第二电压电平的逻辑信号的装置。输出配置包括解复用器，其具有耦合以接收相关逻辑电路的输出信号的输入端，耦合以接收控制信号的控制端以及第一和第二输出端，所述第一解复用器输出端被连接到目标设备。耦合在第二解复用器输出端和目标装置之间的开关具有耦合以接收控制信号的控制端。当控制信号处于第一状态时，开关两端的电压降将第一电压电平的逻辑信号转换为第二电压电平的逻辑信号。当控制信号处于第二状态时，开关不导通，相关逻辑电路的逻辑信号直接提供给目标装置。

6. 发明授权

US06351809B1 Method of disguising a USB port connection 有权
标题翻译：伪装USB端口连接的方法
公开(公告)号：US06351809B1
公开(公告)日：2002-02-26
申请号：US09312035
申请日：1999-05-14
申请人： Donald H. St. Pierre, Jr. , Conrad A. Theron
发明人： Donald H. St. Pierre, Jr. , Conrad A. Theron
IPC分类号： G06F1300
CPC分类号： G06F13/4068
摘要： A method is disclosed for disguising a device's connection to a USB port of, for instance, a host system such as a personal computer or workstation. A device having a microcontroller is connected to a host system using a USB port connection. A switch is coupled between one of the data pins of the USB port and a supply voltage. When the device is connected to the host system via the USB port, the switch is turned off so as not to pull a USB data pin to the supply voltage, and thereby prevents the host system from recognizing that a peripheral device is attached to the USB port. The switch is maintained in a non-conductive state until the microcontroller on the device is booted up and has retrieved identification codes associated with the device and is then turned on. In this manner, the host system does not detect the connection of the device to the host system's USB port until the device is ready to provide suitable identification codes to the host system.
摘要翻译：公开了一种用于伪装设备与例如个人计算机或工作站等主机系统的USB端口的连接的方法。具有微控制器的设备使用USB端口连接连接到主机系统。开关耦合在USB端口的一个数据引脚和电源电压之间。当设备通过USB端口连接到主机系统时，开关被关闭，以便不将USB数据引脚拉到电源电压，从而防止主机系统识别外围设备连接到USB 港口。开关保持在非导通状态，直到设备上的微控制器启动并且已经检索到与设备相关联的识别代码，然后被接通。以这种方式，主机系统不会检测设备与主机系统的USB端口的连接，直到设备准备好向主机系统提供合适的识别码。

7. 发明授权

US06631520B1 Method and apparatus for changing execution code for a microcontroller on an FPGA interface device 有权
标题翻译：用于在FPGA接口设备上改变微控制器的执行代码的方法和装置
公开(公告)号：US06631520B1
公开(公告)日：2003-10-07
申请号：US09312022
申请日：1999-05-14
申请人： Conrad A. Theron , Donald H. St. Pierre, Jr.
发明人： Conrad A. Theron , Donald H. St. Pierre, Jr.
IPC分类号： G06F944
CPC分类号： G06F8/65 , G06F9/24 , G06F15/7867
摘要： A method is disclosed for selectively overlaying portions of a default firmware code for a microcontroller of an FPGA interface device. The FPGA interface device includes a microcontroller, an on-board FPGA, and a memory having first and second pages. Upon initial power-up of the interface device, the default firmware code is loaded into the first memory page. Thereafter, the microcontroller executes instructions received from a host system using the firmware code loaded in the first memory page. Where it is desired to update or modify the firmware code, an overlay code is stored in the second memory page. The overlay code corresponds to selected portions of the default firmware code. Overlay flags are asserted for each of the selected portions of the default firmware code for which a corresponding overlay code is loaded in the second memory page. Then, during execution of subsequent instructions received from the host system, the overlay code is substituted for corresponding portions of the default firmware code for which the overlay flags are asserted.
摘要翻译：公开了一种用于选择性地覆盖FPGA接口设备的微控制器的默认固件代码的部分的方法。 FPGA接口设备包括微控制器，车载FPGA和具有第一和第二页的存储器。在接口设备的初始上电时，默认固件代码被加载到第一存储器页面中。此后，微控制器使用加载在第一存储器页中的固件代码执行从主机系统接收的指令。在希望更新或修改固件代码的地方，重叠代码被存储在第二存储器页面中。覆盖代码对应于默认固件代码的选定部分。对于在第二存储器页面中加载对应的重叠代码的默认固件代码的每个所选部分，覆盖标志被断言。然后，在执行从主机系统接收到的后续指令时，覆盖代码被代替覆盖标志被断言的默认固件代码的相应部分。

8. 发明授权

US06487618B1 Method for resisting an FPGA interface device 有权
标题翻译：抵抗FPGA接口设备的方法
公开(公告)号：US06487618B1
公开(公告)日：2002-11-26
申请号：US09312316
申请日：1999-05-14
申请人： Conrad A. Theron , Donald H. St. Pierre, Jr.
发明人： Conrad A. Theron , Donald H. St. Pierre, Jr.
IPC分类号： G06F1310
CPC分类号： G06F13/4286 , G06F11/1433
摘要： A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.
摘要翻译：公开了一种当板载微控制器不响应于来自主机系统的命令时与具有微控制器的FPGA接口设备进行通信的方法。如果主机系统确定微控制器不响应命令，则主机系统以与通常用于与微控制器通信的波特率显着区别的预定波特率向接口设备发送空字符。接口设备上的逻辑电路监视输入数据的波特率，如果检测到预定波特率的空字符，则逻辑电路切换微控制器的复位引脚。响应于此，微控制器自身重新启动，并且此后能够与主机系统进行通信。通过使用与通常使用的波特率明显区别的其他波特率，向接口设备提供附加命令。

9. 发明授权

US06925583B1 Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device 有权
标题翻译：从具有微控制器的JTAG器件写入到非JTAG器件的结构和方法
公开(公告)号：US06925583B1
公开(公告)日：2005-08-02
申请号：US10043637
申请日：2002-01-09
申请人： Arthur H. Khu , Conrad A. Theron , Farshid Shokouhi , Pushpasheel Tawade
发明人： Arthur H. Khu , Conrad A. Theron , Farshid Shokouhi , Pushpasheel Tawade
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318555
摘要： According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.
摘要翻译：根据本发明，JTAG兼容芯片还具有控制器，该控制器接收在TDI输入引脚上提供的数据，形成并行地址和数据指令，并将数据通过IO引脚传送到非JTAG芯片，而不需要数据通过JTAG兼容芯片的边界扫描寄存器链。该控制器用于对其他芯片进行编程，擦除和读取。对于非JTAG闪存器件，JTAG兼容芯片中的控制器产生必要的编程信号序列，并将其应用于非JTAG芯片，而无需通过JTAG边界扫描电路。

10. 发明授权

US07346784B1 Integrated circuit device programming with partial power 有权
标题翻译：具有部分功率的集成电路器件编程
公开(公告)号：US07346784B1
公开(公告)日：2008-03-18
申请号：US10231694
申请日：2002-08-29
申请人： Conrad A. Theron
发明人： Conrad A. Theron
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/17748 , G01R31/318516 , G11C5/147 , G11C29/12005 , G11C29/48 , H03K19/17736 , H03K19/17784 , H05K1/029 , H05K2201/10053 , H05K2201/10159 , H05K2201/10212 , H05K2201/10689
摘要： A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.
摘要翻译：单独的程序电源输入提供给可编程逻辑阵列的存储器，以允许其独立于印刷电路板电源进行编程。提供了用于隔离阵列可编程逻辑电路的程序电源输入的装置。还提供了用于将存储器与可编程逻辑电路隔离的装置。程序电源不直接或间接连接到可编程逻辑电路，从而允许使用低功率器件对存储器进行编程，而不将印刷电路板连接到电源。

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