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1. 发明申请

US20190214995A1 SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING 审中-公开
公开(公告)号：US20190214995A1
公开(公告)日：2019-07-11
申请号：US16146446
申请日：2018-09-28
申请人： Cypress Semiconductor Corporation
发明人： Bert Sullam , Warren Snyder , Haneef Mohammed
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17744 , H03K19/173 , H03K19/177 , H03K19/17704 , H03K19/1776
摘要： In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

2. 发明授权

US10014865B2 Clock management block 有权
公开(公告)号：US10014865B2
公开(公告)日：2018-07-03
申请号：US14627927
申请日：2015-02-20
申请人： Altera Corporation
发明人： Kent R. Townley , Christopher D. Ebeling , Hamish Fallside , Prasun K. Raha
IPC分类号： G06F1/12 , H04L7/00 , H03L7/00 , H03K19/177 , G06F1/10 , G06F1/06 , G06F1/04 , H03K19/173 , G06F1/08 , G06F17/50 , H03K19/00
CPC分类号： H03K19/17796 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F1/12 , G06F17/5045 , G06F17/5054 , H03K19/00 , H03K19/173 , H03K19/1733 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774
摘要： A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

3. 发明授权

US09954530B2 Implementation of related clocks 有权
公开(公告)号：US09954530B2
公开(公告)日：2018-04-24
申请号：US14599728
申请日：2015-01-19
申请人： Altera Corporation
发明人： Christopher D. Ebeling , Michael Glenn Wrighton , Andrew Caldwell , Kent Townley
IPC分类号： H03K19/173
CPC分类号： H03K19/173
摘要： An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.

4. 发明申请

US20180041215A9 PSOC ARCHITECTURE 有权
公开(公告)号：US20180041215A9
公开(公告)日：2018-02-08
申请号：US14976580
申请日：2015-12-21
申请人： Cypress Semiconductor Corporation
发明人： Warren C. Snyder , Monte Mar
IPC分类号： H03K19/08 , H03K19/173
CPC分类号： H03K19/08 , G06F1/08 , G06F1/32 , G06F15/7867 , G06G7/06 , H03B5/364 , H03K3/012 , H03K3/014 , H03K3/02315 , H03K19/173 , H03K19/1733 , H03K19/177 , H03K19/17736 , H03K19/17748
摘要： An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

5. 发明申请

US20170337963A1 LIGHT EMITTING ELEMENT DRIVING SEMICONDUCTOR INTEGRATED CIRCUIT, LIGHT EMITTING ELEMENT DRIVING DEVICE, LIGHT EMITTING DEVICE, AND VEHICLE 审中-公开
公开(公告)号：US20170337963A1
公开(公告)日：2017-11-23
申请号：US15594816
申请日：2017-05-15
申请人： Rohm Co., Ltd.
发明人： Shinsuke TAKAGIMOTO , Yoshiyuki NAKATANI , Masaaki NAKAYAMA
IPC分类号： G11C11/4063 , H04B10/54 , H04B10/40 , G01R31/02 , H03K19/173 , G01R31/28 , H05B33/08 , H04B10/50
CPC分类号： G11C11/4063 , G01R31/02 , G01R31/2836 , H03K19/173 , H04B10/40 , H04B10/502 , H04B10/54 , H05B33/083 , H05B33/0848 , H05B33/0884 , H05B33/089
摘要： A light emitting element driving semiconductor integrated circuit constitutes at least a part of a light emitting element driving device arranged to drive a series connection unit including a plurality of light emitting elements. The light emitting element driving semiconductor integrated circuit includes a single-element short-circuit detection unit arranged to detect that one of the plurality of light emitting elements is short-circuited, and a control unit arranged to control a power element of the light emitting element driving device so that current supplied from the light emitting element driving device to the series connection unit is increased, when the single-element short-circuit detection circuit detects that one of the plurality of light emitting elements is short-circuited.

6. 发明授权

US09817790B2 Multi-processor with selectively interconnected memory units 有权
公开(公告)号：US09817790B2
公开(公告)日：2017-11-14
申请号：US15052730
申请日：2016-02-24
申请人： PACT XPP TECHNOLOGIES AG
发明人： Martin Vorbach
IPC分类号： H03K19/173 , G06F15/78 , G06F13/16 , G06F9/30 , G06F13/36 , G06F13/40
CPC分类号： G06F15/7867 , G06F9/30145 , G06F13/16 , G06F13/36 , G06F13/4068 , H03K19/173
摘要： A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

7. 发明申请

US20170316309A1 SELF-ORGANIZING LOGIC GATES AND CIRCUITS AND COMPLEX PROBLEM SOLVING WITH SELF-ORGANIZING CIRCUITS 有权
公开(公告)号：US20170316309A1
公开(公告)日：2017-11-02
申请号：US15645872
申请日：2017-07-10
申请人： The Regents of The University of California
发明人： Massimiliano Di Ventra , Fabio Lorenzo Traversa
IPC分类号： G06N3/063 , G06N3/08
CPC分类号： G06N3/063 , G06G7/122 , G06N3/08 , H03K19/173 , H03K19/20
摘要： Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal. A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.

8. 发明授权

US09805153B2 PLD editor and method for editing PLD code 有权
公开(公告)号：US09805153B2
公开(公告)日：2017-10-31
申请号：US14828116
申请日：2015-08-17
申请人： ROCKWELL AUTOMATION TECHNOLOGIES, INC.
发明人： Tao Song , Zhen Wei , Fabio Malaspina , Hongrui Li , Zhiyan Chen
IPC分类号： G06F11/07 , G06F7/38 , H03K19/173 , G06F17/50
CPC分类号： G06F17/5054 , G06F8/34 , H03K19/017581 , H03K19/173
摘要： Technology for editing PLD code to be programmed into a PLD are provided. The technology includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block parameters for each logic instruction block, with the PLD code being intended for programming into the PLD, compare the one or more logic instruction blocks of the PLD code to a subset of the library of logic instruction blocks applicable to the PLD according to the library of PLD devices, determine inconsistent logic instruction blocks of the one or more logic instruction blocks, indicate the inconsistent logic instruction blocks, and correct the inconsistent logic instruction blocks using the subset of the library of logic instruction blocks.

9. 发明授权

US09755646B2 Input/output buffer circuit for avoiding malfunctioning in processing signals 有权
公开(公告)号：US09755646B2
公开(公告)日：2017-09-05
申请号：US15011653
申请日：2016-01-31
申请人： Nuvoton Technology Corporation
发明人： Cheng-Chih Wang
IPC分类号： H03K3/00 , H03K19/173 , H03K19/0185
CPC分类号： H03K19/173 , G11C13/0002 , G11C14/0054 , H03K19/018507 , H03K19/018521
摘要： An input/output (I/O) buffer circuit includes an I/O unit, a first register and a second register. The I/O unit selectively transmits digital signals and analog signals according to a first enable signal, and selectively receives signals and outputs signals at an I/O terminal according to a second enable signal. The first register latches a first control signal received before power is turned off, and outputs the first enable signal corresponding to the first control signal to the I/O unit when power is turned on. The second register latches a second control signal received before power is turned off, and outputs the second enable signal corresponding to the second control signal to the I/O unit when power is turned on.

10. 发明授权

US09576095B1 Partial reconfiguration compatibility detection in an integrated circuit device 有权
标题翻译：集成电路器件中的部分重配置兼容性检测
公开(公告)号：US09576095B1
公开(公告)日：2017-02-21
申请号：US14447279
申请日：2014-07-30
申请人： Altera Corporation
发明人： Yin Chong Hew , Paul Mark Leventis
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5068 , G06F17/5054 , H03K19/173
摘要： Methods for partial reconfiguration compatibility detection in an integrated circuit device are disclosed. A disclosed method includes storing a unique identifier that identifies a partial reconfiguration region of the integrated circuit device in a storage circuit. A control circuit may receive an input partial reconfiguration data that activates the operations of the partial reconfiguration region. The method further includes comparing the input partial reconfiguration data to the stored unique identifier prior to activating the operations of the partial reconfiguration region of the integrated circuit device. The input partial reconfiguration data may contain an associated identifier that is derived from the unique identifier during a design compilation operation of the integrated circuit device.
摘要翻译：公开了一种用于集成电路器件中部分重配置兼容性检测的方法。所公开的方法包括将识别集成电路设备的部分重新配置区域的唯一标识符存储在存储电路中。控制电路可以接收激活部分重新配置区域的操作的输入部分重配置数据。该方法还包括在激活集成电路设备的部分重新配置区域的操作之前将输入的部分重新配置数据与存储的唯一标识符进行比较。输入部分重新配置数据可以包含在集成电路设备的设计编译操作期间从唯一标识符导出的相关联的标识符。

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