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1. 发明授权

US07620883B1 Techniques for mitigating, detecting, and correcting single event upset effects 有权
标题翻译：减轻，检测和纠正单事件不安效应的技术
公开(公告)号：US07620883B1
公开(公告)日：2009-11-17
申请号：US11388897
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

2. 发明授权

US07512871B1 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07512871B1
公开(公告)日：2009-03-31
申请号：US11388742
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G06F11/08 , H03D3/24 , G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

3. 发明授权

US07310759B1 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07310759B1
公开(公告)日：2007-12-18
申请号：US11388728
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G01R31/28 , H03K17/693
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

4. 发明授权

US07036059B1 Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07036059B1
公开(公告)日：2006-04-25
申请号：US09783821
申请日：2001-02-14
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. The mitigation techniques include: triple redundancy of a logic path is extended the length of the FPGA to avoid weak points susceptible to SEU effects; triple logic module and feedback redundancy provides redundant hardwired voter circuits at redundant logic outputs and voter circuits in feedback loops to ensure each logic module will receive accurate current state data even if it was upset by an SEU; enhanced triple device redundancy using three FPGAs is introduced, with a fourth device acting as a voting circuit and employing triple logic module and feedback redundancy of the second technique to provide nine instances of the user's logic and ensure complete accuracy in the system; critical redundant outputs are wire-ANDed together to ensure the output is asserted only when the redundant logic modules agree it should be asserted; redundant dual port RAMs are provided, with one port of each RAM dedicated to refreshing data and the remaining port of each RAM being available for use with the user's logic; and redundant clock delay locked loops (DLL) are provided and each DLL is monitored and reset if it does not remain in phase with the majority of the DLLs. The detection techniques include: configuration memory readback wherein a checksum for the expected value is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. The correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated rather than actually detected SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展了FPGA的长度，以避免易受SEU影响的弱点; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的硬连线选举电路，以确保每个逻辑模块即使被SEU扰乱也将接收准确的当前状态数据; 引入了使用三个FPGA的增强三重设备冗余，第四个设备充当投票电路，采用第三种逻辑模块和第二种技术的反馈冗余，提供用户逻辑的九个实例，并确保系统的完整准确性; 关键的冗余输出线对并在一起，以确保输出仅在冗余逻辑模块同意应被断言时被置位; 提供冗余双端口RAM，每个RAM的一个端口专用于刷新数据，并且每个RAM的剩余端口可用于与用户的逻辑一起使用; 并提供冗余时钟延迟锁定环（DLL），并且如果每个DLL与大多数DLL不保持同步，则监视并重置每个DLL。检测技术包括：配置存储器回读，其中验证期望值的校验和; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期而不是实际检测到的SEU来重新组态部分配置数据和“擦除”。

5. 发明授权

US07383479B1 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays 有权
标题翻译：在使用基于SRAM的现场可编程门阵列的系统中减轻，检测和纠正单事件扰乱效应的技术
公开(公告)号：US07383479B1
公开(公告)日：2008-06-03
申请号：US11389349
申请日：2006-03-24
申请人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
发明人： Carl H. Carmichael , Phil Edward Brinkley, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/106 , G06F11/1004 , G11C11/4125
摘要： SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
摘要翻译：公布了SEU缓解，检测和校正技术。缓解技术包括：逻辑路径的三重冗余扩展FPGA的长度; 三逻辑模块和反馈冗余在冗余逻辑输出和反馈回路中的选举电路中提供冗余的选举电路; 引入使用三个FPGA的增强的三重设备冗余，以提供用户逻辑的九个实例; 关键冗余输出与线并联在一起; 冗余双端口RAM，一个端口专用于刷新数据; 并且如果每个DLL不与大多数DLL保持同步，则监视并重置冗余时钟延迟锁定环（DLL）。检测技术包括：校验和被验证的配置存储器回读; 单独的FPGA执行相邻FPGA的配置存储器的回读; 并且FPGA执行其配置存储器阵列的自回读。校正技术包括基于预期的SEU重新配置部分配置数据和“擦除”。

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