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1. 发明申请

US20190095298A1 AUTOMATED ANALOG FAULT INJECTION 审中-公开
公开(公告)号：US20190095298A1
公开(公告)日：2019-03-28
申请号：US15713090
申请日：2017-09-22
申请人： Analog Devices Global Unlimited Company
发明人： Courtney E. FRICANO , Paul P. WRIGHT , David BROWNELL
IPC分类号： G06F11/22 , G01R31/3183 , G06F17/50 , G01R31/28
CPC分类号： G06F11/2252 , G01R31/2846 , G01R31/31835 , G06F17/5022 , G06F2217/70
摘要： Systems and methods are provided for automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.

2. 发明申请

US20170212972A1 LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS LOW VOLTAGE CHECK FOR LIMIT OF OPERATION 审中-公开
公开(公告)号：US20170212972A1
公开(公告)日：2017-07-27
申请号：US15288912
申请日：2016-10-07
申请人： Austemper Design Systems Inc.
发明人： Sanjay Pillay
IPC分类号： G06F17/50 , H03K19/21 , H03K19/00
CPC分类号： G11C29/12015 , G06F17/5009 , G06F17/5022 , G06F17/5045 , G06F2217/70 , G11C11/412 , G11C29/52 , G11C29/54 , H03K19/0008 , H03K19/21
摘要： Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation of the design are provided. One such method involves the addition of a plurality of bits for sequential elements in the design including set of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single or double bit error in the sequential elements, starting at a nominal voltage of operation and gradually lowering the voltage setting till the first error is detected in the sequential elements, increasing the operating voltage by predetermined step above the voltage of first fail to achieve the optimal lowest voltage of correct operation of the design, storing this optimal voltage setting in a non-volatile memory for subsequent use.

3. 发明授权

US09583218B1 Configurable register circuitry for error detection and recovery 有权
标题翻译：用于错误检测和恢复的可配置寄存器电路
公开(公告)号：US09583218B1
公开(公告)日：2017-02-28
申请号：US14252752
申请日：2014-04-14
申请人： Altera Corporation
发明人： Michael D. Hutton , Martin Langhammer
IPC分类号： G11C29/56 , G06F11/07 , G06F11/14 , G06F11/10 , G06F11/27 , G06F9/30 , G06F17/50 , H04L7/04 , H04L1/00 , G11C11/412 , G11C29/04
CPC分类号： G11C29/56008 , G06F1/10 , G06F9/30141 , G06F11/0751 , G06F11/10 , G06F11/1451 , G06F11/27 , G06F17/5054 , G06F2217/70 , G11C11/4125 , G11C2029/0409 , G11C2029/0411 , G11C2207/104 , H01L2924/00 , H03K19/177 , H03K19/17704 , H04L1/004 , H04L7/042
摘要： Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.
摘要翻译：诸如专用集成电路或可编程逻辑器件的集成电路可以包括诸如可配置寄存器电路的顺序元件。这种可配置寄存器电路可以作为由可选择的时钟信号控制的独立寄存器或作为具有错误检测和纠错能力的单个寄存器来操作。例如，当作为具有错误检测和错误校正电路的单个寄存器操作时，可配置寄存器电路可以检测和纠正由制造和环境变化引起的运行时错误，从而允许增加控制寄存器的时钟速率。如果需要，可配置的寄存器电路可以被配置为检测单个事件的不匹配，这可以实现安全的有限状态机。

4. 发明授权

US09569573B1 RAS evaluation for circuit element 有权
标题翻译： RAS评估电路元件
公开(公告)号：US09569573B1
公开(公告)日：2017-02-14
申请号：US15062699
申请日：2016-03-07
申请人： International Business Machines Corporation
发明人： Christian Jacobi , Udo Krautz
IPC分类号： G06F17/50 , H03M13/00
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/70
摘要： A computer-implemented method includes identifying an electronic circuit, which includes a plurality of circuit elements and is based on a circuit design. The circuit design includes structural information and logical information. The method generates a first verification model for the circuit design. The verification model includes a plurality of error report signal paths for each of the plurality of circuit elements. The method identifies a first circuit element output based on the plurality of error report signal paths. The method sets output for at least one of the first plurality of circuit elements to a fixed value. The method generates a second circuit element output based on the plurality of error report signal paths and setting output for at least one of the first plurality of circuit elements to a fixed value. The method determines a difference between the first circuit element output and the second circuit element output.
摘要翻译：计算机实现的方法包括识别包括多个电路元件并且基于电路设计的电子电路。电路设计包括结构信息和逻辑信息。该方法为电路设计生成第一个验证模型。验证模型包括用于多个电路元件中的每一个的多个错误报告信号路径。该方法基于多个错误报告信号路径来识别第一电路元件输出。该方法将第一多个电路元件中的至少一个的输出设置为固定值。该方法基于多个误差报告信号路径生成第二电路元件输出，并将第一多个电路元件中的至少一个电路元件的输出设置为固定值。该方法确定第一电路元件输出和第二电路元件输出之间的差异。

5. 发明授权

US09507895B2 Simulation apparatus and simulation method for determining soft error rates for a configured model 有权
标题翻译：用于确定配置模型的软错误率的仿真设备和仿真方法
公开(公告)号：US09507895B2
公开(公告)日：2016-11-29
申请号：US13702636
申请日：2011-05-13
申请人： Tadanobu Toba , Kenichi Shimbo , Hidefumi Ibe , Hideki Osaka
发明人： Tadanobu Toba , Kenichi Shimbo , Hidefumi Ibe , Hideki Osaka
IPC分类号： G06F17/50 , G06G7/62 , G01R31/3181
CPC分类号： G06F17/5036 , G01R31/31816 , G06F17/5022 , G06F2217/70
摘要： A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
摘要翻译：模拟装置包括：离散事件模拟部分，用于执行基于属性信息定义的配置模型的分量的离散类型模拟，所述属性信息是关于所定义的配置模型的组件的部分的信息，以及示出组件之间的连接关系的连接信息的定义配置模型; 以及软错误率计算处理部，基于离散事件模拟部的模拟结果和属性信息中的软错误率的数据来计算定义的配置模型的软错误率。

6. 发明授权

US09424382B1 Method and apparatus for providing fault tolerance through compilation diversity 有权
标题翻译：通过编译多样性提供容错的方法和装置
公开(公告)号：US09424382B1
公开(公告)日：2016-08-23
申请号：US14085757
申请日：2013-11-20
申请人： Altera Corporation
发明人： Adam Titley
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/06 , G06F2217/70
摘要： A method for designing a system on a target device includes synthesizing a logic representation of a processing channel from a description of the processing channel in hardware description language (HDL) according to a first set of constraints. A logic representation for a redundant processing channel is synthesized from the description of the processing channel in HDL according to a second set of constraints. The processing channel and the redundant processing channel are placed and routed.
摘要翻译：用于在目标设备上设计系统的方法包括根据第一组约束从硬件描述语言（HDL）中的处理通道的描述中合成处理通道的逻辑表示。根据第二组约束，从HDL中的处理信道的描述合成用于冗余处理信道的逻辑表示。处理通道和冗余处理通道被放置和布线。

7. 发明授权

US09292399B2 Design-Based weighting for logic built-in self-test 有权
标题翻译：基于设计的加权逻辑内置自检
公开(公告)号：US09292399B2
公开(公告)日：2016-03-22
申请号：US14501122
申请日：2014-09-30
申请人： International Business Machines Corporation
发明人： Gregory J. Cook , Timothy J. Koprowski , Mary P. Kusko , Cedric Lichtenau
IPC分类号： G06F11/27 , G01R31/3187 , G06F17/50
CPC分类号： G06F11/27 , G01R31/3187 , G06F17/50 , G06F17/5068 , G06F2217/14 , G06F2217/70
摘要： Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.
摘要翻译：实施例涉及用于逻辑内置自检（LBIST）的基于设计的加权。一个方面包括用于实现LBIST的基于设计的权重的计算机程序产品。计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括通过处理电路分析多个集成电路设计组织单元，以确定当应用于随机模式发生器时提供最高级别的故障覆盖的集成电路设计组织单元的首选权重。基于确定优选权重，处理电路产生集成电路布局，该集成电路布局包括多个加权测试路径，以分别向集成电路设计组织单元施加优选权重。集成电路布局被并入被测器件中。

8. 发明申请

US20160063172A1 Connectivity-Aware Layout Data Reduction For Design Verification 有权
标题翻译：连接感知布局数据缩减用于设计验证
公开(公告)号：US20160063172A1
公开(公告)日：2016-03-03
申请号：US14663275
申请日：2015-03-19
申请人： Mentor Graphics Corporation
发明人： Yi-Ting Lee , Sridhar Srinivasan , Hung-Hsu Feng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/70
摘要： Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.
摘要翻译：所公开技术的方面涉及布局数据的连通性意识降低的技术。通过所公开的技术的各种实施方案，在包括网表信息和布局数据的电路设计中选择感兴趣的电路元件。至少基于感兴趣的电路元件的引脚，确定所关心的电路元件或两个感兴趣的网络。然后确定包括针对感兴趣的电路元件的至少一个引脚识别的感兴趣的单元，感兴趣的电路元件或二者的两个细胞。基于感兴趣的网络和感兴趣的单元格，选择布局几何元素并进行设计验证。对于静电放电（ESD）保护验证，感兴趣的电池还可以包括在顶部金属层上包括电力供应栅格的部分的电池。

9. 发明授权

US08640063B1 Method for synthesizing soft error tolerant combinational circuits 失效
标题翻译：软错误容错组合电路的合成方法
公开(公告)号：US08640063B1
公开(公告)日：2014-01-28
申请号：US13732241
申请日：2012-12-31
申请人： King Fahd University of Petroleum and Minerals
发明人： Aiman Helmi El-Maleh , Khaled Abdel-Karim Daud
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/70
摘要： The method for synthesizing soft error tolerant combinational circuits includes the step of inputting a combinational circuit to a combinational circuit analyzer for analysis. The analyzer then extracts smaller sub-circuits from said combinational circuit, computes probabilities of input vectors to occur for each of the smaller sub-circuits, produces new multi-level sub-circuits from the extracted sub-circuit, and maximizes logical fault masking against the occurrence of a single fault applied to the new multi-level sub-circuits, the maximizing being based on probabilities of sub-circuit input vectors to occur. Finally, the analyzer merges the new multi-level sub-circuits back to the original inputted combinational circuit.
摘要翻译：用于合成软错误容错组合电路的方法包括将组合电路输入到组合电路分析器进行分析的步骤。分析仪然后从所述组合电路中提取较小的子电路，计算出每个较小子电路的输入向量的概率，从提取的子电路产生新的多电平子电路，并使逻辑故障屏蔽最大化发生单个故障应用于新的多电平子电路，最大化是基于发生的子电路输入向量的概率。最后，分析仪将新的多电平子电路合并回原始输入的组合电路。

10. 发明申请

US20130305199A1 IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGATION IN FPGA 有权
标题翻译：用于FPGA中软错误减少的内置重建和重新安装技术
公开(公告)号：US20130305199A1
公开(公告)日：2013-11-14
申请号：US13850898
申请日：2013-03-26
申请人： The Regents of The University of California
发明人： Lei He , Ju-Yueh Lee , Zhe Feng , Naifeng Jing
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/70 , H03K19/0033 , H03K19/00369
摘要： In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV), which reconfigure LUT functions only, and can be applied to any FPGA architecture. In addition, for FPGAs with a decomposable LUT architecture (e.g., dual-output LUTs) an in-place decomposition (IPD) method is described for remapping a LUT function into multiple smaller functions leveraging the unused outputs of the LUT, and making use of built-in hard macros in programmable-logic blocks (PLBs) such as carry chain or adder. Methods are applied in-place to mapped circuits before or after routing without affecting placement, routing, and design closure.
摘要翻译：基于静态存储器（SRAM）的现场可编程门阵列（FPGA）的就地再合成，以降低对单事件扰乱（SEU）的灵敏度。描述了重新合成和重新映射，其具有低的窃听和改进的FPGA设计，而不需要重新路由的LUT的LUT。这些方法包括就地重新配置（IPR），就地X填充（IPF）和就地倒置（IPV），其仅重新配置LUT功能，并且可以应用于任何FPGA架构。此外，对于具有可分解LUT架构的FPGA（例如，双输出LUT），描述了一种就地分解（IPD）方法，用于将LUT功能重新映射到利用LUT的未使用输出的多个较小功能中，并利用内置硬宏，可编程逻辑块（PLB），如进位链或加法器。方法在路由之前或路由后适用于映射电路，而不影响布局，路由和设计关闭。

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