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1. 发明授权

US06823411B2 N-way psuedo cross-bar having an arbitration feature using discrete processor local busses 失效
标题翻译：具有使用离散处理器局部总线的仲裁功能的N路伪装横杆
公开(公告)号：US06823411B2
公开(公告)日：2004-11-23
申请号：US10059558
申请日：2002-01-30
申请人： Richard Gerard Hofmann , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Barry Joe Wolford
IPC分类号： G06F1314
CPC分类号： G06F13/364
摘要： A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus master in the system is coupled to all bus arbiters in the system, so that each bus master can access a corresponding bus slave concurrently as well as sequentially. Such concurrent communication carries not only read and/or write data but also a target address of the corresponding bus slave, thereby enabling true concurrency in data communication between bus masters and bus slaves.
摘要翻译：提供总线架构以通过在片上系统（SOC）系统中具有两个或多个总线仲裁器来促进独立总线主机和独立总线从站之间的通信。系统中的每个总线主机耦合到系统中的所有总线仲裁器，使得每个总线主机可以同时和顺序地访问相应的总线从站。这种并发通信不仅携带读取和/或写入数据，而且还携带相应总线从站的目标地址，从而在总线主站和总线从站之间的数据通信中实现真正的并发。

2. 发明授权

US06822654B1 Memory controller chipset 有权
标题翻译：内存控制器芯片组
公开(公告)号：US06822654B1
公开(公告)日：2004-11-23
申请号：US10038700
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Yutaka Takahashi , Steven Todd Weybrew , Derek Fujio Iwamoto , David Ligon
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Yutaka Takahashi , Steven Todd Weybrew , Derek Fujio Iwamoto , David Ligon
IPC分类号： G06F1314
CPC分类号： G06F13/1668
摘要： At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.
摘要翻译：本文中描述了具有至少一个主机处理器和主机存储器的计算机系统中的芯片组的至少一个芯片。在本发明的一个方面中，示例性芯片包括互连，耦合到互连的存储器接口，存储器接口，提供对主机存储器的访问和控制存储器刷新和存储器访问，耦合到互连的主机接口，主机接口提供对主处理器的访问，以及耦合到互连的可编程媒体处理器，媒体处理器通过主机接口访问主机，并且媒体处理器通过存储器接口访问主机存储器，其中媒体处理器处理基于时间的媒体。

3. 发明授权

US06820151B2 Starvation avoidance mechanism for an I/O node of a computer system 有权
标题翻译：计算机系统的I / O节点的饥饿避免机制
公开(公告)号：US06820151B2
公开(公告)日：2004-11-16
申请号：US09978379
申请日：2001-10-15
申请人： Stephen C. Ennis
发明人： Stephen C. Ennis
IPC分类号： G06F1314
CPC分类号： H04L47/6285 , H04L47/50
摘要： A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.
摘要翻译：用于计算机系统的输入/输出节点的饥饿避免机制。调度器单元包括第一缓冲电路和第二缓冲电路。第一缓冲电路包括用于存储从第一源接收的所选控制命令的第一多个缓冲器，并且第二缓冲电路包括用于存储从第二源接收的所选控制命令的第二多个缓冲器。调度器还包括耦合到第一缓冲电路和第二缓冲电路的仲裁电路。仲裁电路可以被配置为在存储在第一缓冲器电路中的控制命令和存储在第二缓冲器电路中的控制命令之间进行仲裁。选择的仲裁周期的结果可以取决于由于不可用目的地而阻止来自缓冲器中的给定缓冲器的控制命令的次数。

4. 发明授权

US06801967B2 Wireless mouse unit, wireless mouse and receiver 失效
标题翻译：无线鼠标单元，无线鼠标和接收器
公开(公告)号：US06801967B2
公开(公告)日：2004-10-05
申请号：US09866648
申请日：2001-05-30
申请人： Shuji Nakamura , Tamotsu Koike , Kazuhiro Watanabe
发明人： Shuji Nakamura , Tamotsu Koike , Kazuhiro Watanabe
IPC分类号： G06F1314
CPC分类号： G06F3/038 , G06F3/03543 , G06F2203/0384
摘要： A wireless mouse unit has a wireless mouse generating signals for moving a cursor across a display screen, a rechargeable secondary battery cell built into the wireless mouse, and a receiver for receiving the signals transmitted from the wireless mouse, the receiver electrically connected to and powered by a computer via a cable. The receiver includes a charging terminal for recharging the rechargeable battery when the wireless mouse is placed in the receiver, eliminating the need for a special charger to recharge the rechargeable secondary battery cell built into the wireless mouse.
摘要翻译：无线鼠标单元具有无线鼠标，用于产生用于在显示屏幕上移动光标的信号，内置于无线鼠标中的可再充电二次电池单元，以及用于接收从无线鼠标发送的信号的接收器，接收器电连接到电源通过电脑通过电缆。接收机包括充电终端，用于当无线鼠标放置在接收器中时对可再充电电池进行再充电，从而无需专门的充电器对内置于无线鼠标中的可充电二次电池进行再充电。

5. 发明授权

US06789056B2 DSP interface for packet processing 失效
标题翻译： DSP接口用于数据包处理
公开(公告)号：US06789056B2
公开(公告)日：2004-09-07
申请号：US10334225
申请日：2002-12-31
申请人： Bapi Vinnakota , Sameer Nanavati , Saurin Shah , Nicholas E. Duresky
发明人： Bapi Vinnakota , Sameer Nanavati , Saurin Shah , Nicholas E. Duresky
IPC分类号： G06F1314
CPC分类号： H04L12/66
摘要： A method, apparatus, and system for communicating between a digital signal processor (DSP) and a packet processor.
摘要翻译：一种用于在数字信号处理器（DSP）和分组处理器之间通信的方法，装置和系统。

6. 发明授权

US06782441B1 Arbitration method and apparatus 有权
标题翻译：仲裁方法和设备
公开(公告)号：US06782441B1
公开(公告)日：2004-08-24
申请号：US09697222
申请日：2000-10-26
申请人： Hien H. Nguyen , Don M. Morrier
发明人： Hien H. Nguyen , Don M. Morrier
IPC分类号： G06F1314
CPC分类号： G06F9/526
摘要： An arbitration method and mechanism assigning priority to one of a combination of requesters. A priority vector for the combination of requesters has a sequential list of requester identifiers. Upon receiving requests from the combination of requesters, the corresponding priority vector is referred to and the next requester identifier on this list is selected. Priority is awarded to the requester corresponding to that requester identifier. A priority vector is preferably provided for each possible combination of multiple requesters. The list of requester identifiers in each priority vector may be advantageously programmable. Preferably, all requester identifiers for a single requester are not provided in a contiguous clump within a given priority vector.
摘要翻译：一种仲裁方法和机制，将优先级分配给请求者的组合之一。请求者组合的优先级向量具有请求者标识符的顺序列表。在接收到请求者的组合的请求时，参考相应的优先级向量，并且选择该列表上的下一个请求者标识符。优先级被授予与该请求者标识符相对应的请求者。优选地，向多个请求者的每个可能的组合提供优先权向量。每个优先级向量中的请求者标识符的列表可以是有利的可编程的。优选地，单个请求者的所有请求者标识符不在给定优先级向量内的连续群中提供。

7. 发明授权

US06772239B2 Computer product and method for smart card 失效
标题翻译：智能卡计算机产品和方法
公开(公告)号：US06772239B2
公开(公告)日：2004-08-03
申请号：US09862787
申请日：2001-05-19
申请人： Philip Sydney Langton
发明人： Philip Sydney Langton
IPC分类号： G06F1314
CPC分类号： G06F9/24
摘要： A system, method and computer program for smart card with memory is disclosed. A very low cost approach to embodiment is disclosed, making use of a micro-controller with a FLASH memory or a WORM memory. An approach to programming a flash memory under the control of instructions within that memory itself is disclosed. In utilizing the invention, it is possible to build smart cards at a lower cost than heretofore.
摘要翻译：公开了一种具有存储器的智能卡的系统，方法和计算机程序。公开了一种非常低成本的实施方式，利用具有闪速存储器或WORM存储器的微控制器。公开了一种在该存储器本身内的指令控制下对闪速存储器进行编程的方法。利用本发明，可以以比迄今为止更低的成本构建智能卡。

8. 发明授权

US06760802B2 Time-out counter for multiple transaction bus system bus bridge 有权
标题翻译：多事务总线系统总线桥的超时计数器
公开(公告)号：US06760802B2
公开(公告)日：2004-07-06
申请号：US09932379
申请日：2001-08-17
申请人： Steven R. Jahnke , Hiromichi Hamakawa
发明人： Steven R. Jahnke , Hiromichi Hamakawa
IPC分类号： G06F1314
CPC分类号： G06F13/24 , G06F13/3625 , G06F13/4031
摘要： The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus device if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus. Address and data FIFO buffers are used for writes to a second bus device.
摘要翻译：本发明的超时计数器提供总线桥接器中的能力，用于第一总线主机在第二总线设备读取时产生超时中断，如果在一定时间段内没有给予第二总线控制，第二班车仲裁时间过长。超时计数器可编程高达16位，允许软件选择超时长度。如果所使用的仲裁的方式否则允许第二总线主机对第一总线进行绝对控制，则该超时功能是有用的。地址和数据FIFO缓冲区用于写入第二总线设备。

9. 发明授权

US06751680B2 Protected control of devices by user applications in multiprogramming environments 有权
标题翻译：用户应用程序在多程序设计环境中对设备进行受保护的控制
公开(公告)号：US06751680B2
公开(公告)日：2004-06-15
申请号：US10082663
申请日：2002-02-25
申请人： Alan B. Langerman , David A. Ford
发明人： Alan B. Langerman , David A. Ford
IPC分类号： G06F1314
CPC分类号： G06F12/145 , G06F12/1081
摘要： A user program directly accesses a storage device for I/O operations, bypassing the operating system. The user registers a virtual memory region and an “extent”, or region, of the storage device with a host bus adapter. A virtual interface is created between the user and the storage device including a queue for transmitting commands from the user to the storage device. To perform I/O, the user creates a descriptor including command information identifying the type of I/O operation, a buffer handle identifying the registered virtual memory region, virtual memory address information identifying the locations of data buffers in the registered virtual memory region to be used for the I/O operation, an extent handle identifying the registered extent, and disk address information identifying an area within the registered extent to or from which data is to be written or read. The user posts this descriptor to the virtual interface by placed it on the associated queue. The adapter reads the descriptor and verifies that the descriptor and the data buffers are located within the registered virtual memory region identified by the buffer handle. The adapter also verifies that the area on the storage device identified by the disk address information is within the registered extent identified by the extent handle. If both of these verification steps succeed, then the I/O command is forwarded to the storage device. If either verification step fails, then the command is not forwarded, and an indication of the failure is returned to the user or the operating system.
摘要翻译：用户程序直接访问存储设备进行I / O操作，绕过操作系统。用户使用主机总线适配器注册存储设备的虚拟内存区域和“范围”或区域。在用户和存储设备之间创建虚拟接口，包括用于从用户向存储设备发送命令的队列。为了执行I / O，用户创建包括识别I / O操作类型的命令信息，识别注册的虚拟存储器区域的缓冲器句柄，识别注册的虚拟存储器区域中的数据缓冲器的位置的虚拟存储器地址信息的描述符，用于I / O操作，识别注册范围的扩展名句柄，以及标识要写入或读取数据的注册范围内的区域的磁盘地址信息。用户通过将该描述符放置在相关联的队列上来将该描述符发布到虚拟接口。适配器读取描述符并且验证描述符和数据缓冲器位于由缓冲器句柄标识的注册的虚拟存储器区域内。适配器还验证由磁盘地址信息识别的存储设备上的区域在扩展区段识别的注册范围内。如果这两个验证步骤都成功，则将I / O命令转发到存储设备。如果任一验证步骤失败，则不转发该命令，并且向用户或操作系统返回失败指示。

10. 发明授权

US06748469B1 Parallel/serial SCSI with legacy support 失效
标题翻译：具有传统支持的并行/串行SCSI
公开(公告)号：US06748469B1
公开(公告)日：2004-06-08
申请号：US09774501
申请日：2001-01-31
申请人： Barry Caldwell , Craig C. McCombs
发明人： Barry Caldwell , Craig C. McCombs
IPC分类号： G06F1314
CPC分类号： G06F13/387
摘要： The present invention is directed to a parallel/serial SCSI with legacy support. A small computer system interface (SCSI) converter module may include a small computer system interface (SCSI) converter. The converter is suitable for converting a parallel bus structure to a serial bus structure, and the converter is also suitable for supporting a parallel bus structure to a parallel bus structure.
摘要翻译：本发明涉及具有传统支持的并行/串行SCSI。小型计算机系统接口（SCSI）转换器模块可以包括小型计算机系统接口（SCSI）转换器。该转换器适用于将并行总线结构转换为串行总线结构，并且转换器也适用于将并行总线结构支持到并行总线结构。

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