专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06553523B1 System and method for verifying configuration of a programmable logic device 有权
标题翻译：用于验证可编程逻辑器件的配置的系统和方法
公开(公告)号：US06553523B1
公开(公告)日：2003-04-22
申请号：US09374251
申请日：1999-08-13
申请人： Jeffrey V. Lindholm , Chakravarthy K. Allamsetty
发明人： Jeffrey V. Lindholm , Chakravarthy K. Allamsetty
IPC分类号： G01R3128
CPC分类号： G01R31/318516
摘要： A system and method utilize bitmaps for verifying configuration of a programmable logic device (PLD). A configuration bitstream containing configuration commands and data is converted to a configuration bitmap. The configuration bitstream is downloaded to PLD, thus programming the PLD. Readback commands and data read back from the PLD are used to generate a readback bitstream. The readback bitstream is then converted to a readback bitmap. Bits at corresponding cell locations in the readback bitmap and the configuration bitmap are compared. An error signal is output if the bits are different. In one embodiment, a mask bitmap is generated to indicate which cell locations are non-configuration memory cells and thus need not be compared.
摘要翻译：系统和方法利用位图来验证可编程逻辑器件（PLD）的配置。包含配置命令和数据的配置比特流被转换为配置位图。将配置比特流下载到PLD，从而对PLD进行编程。从PLD回读的回读命令和数据用于生成回读比特流。然后将回读比特流转换为回读位图。比较回读位图和配置位图中相应单元格位置的位。如果位不同，则输出错误信号。在一个实施例中，生成掩码位图以指示哪些单元位置是非配置存储器单元，因此不需要进行比较。

2. 发明授权

US06618686B2 System and method for testing a circuit implemented on a programmable logic device 有权
标题翻译：用于测试在可编程逻辑器件上实现的电路的系统和方法
公开(公告)号：US06618686B2
公开(公告)日：2003-09-09
申请号：US09311628
申请日：1999-05-14
申请人： Chakravarthy K. Allamsetty
发明人： Chakravarthy K. Allamsetty
IPC分类号： G01R2728
CPC分类号： G01R31/31915 , G01R31/318516
摘要： A system and method for testing a circuit implemented on a programmable logic device. A host processor is coupled to the programmable logic device via an interface device, which has a plurality of signal pins for configuring the programmable logic device. Selected pins of the interface device are connected to selected input pins of the programmable logic device. Test vectors from the host processor are applied to the selected input pins of the programmable logic device via the interface device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.
摘要翻译：一种用于测试在可编程逻辑器件上实现的电路的系统和方法。主机处理器经由接口设备耦合到可编程逻辑器件，接口器件具有用于配置可编程逻辑器件的多个信号引脚。接口设备的所选引脚连接到可编程逻辑器件的选定输入引脚。来自主处理器的测试向量经由接口装置应用于可编程逻辑器件的选定输入引脚，并且分析出现在器件的一个或多个输出引脚上的一个或多个信号的状态。

3. 发明授权

US06425077B1 System and method for reading data from a programmable logic device 有权
标题翻译：用于从可编程逻辑器件读取数据的系统和方法
公开(公告)号：US06425077B1
公开(公告)日：2002-07-23
申请号：US09312024
申请日：1999-05-14
申请人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
发明人： Thach-Kinh Le , Chakravarthy K. Allamsetty , Carl H. Carmichael , Arun K. Mandhania , Donald H. St. Pierre, Jr. , Conrad A. Theron
IPC分类号： G06F300
CPC分类号： G01R31/31919 , G01R31/318516
摘要： A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.
摘要翻译：一种用于从可编程逻辑器件（PLD）读回数据的系统和方法。构成具有一个或多个时钟偏移值的时钟偏移表。每个时钟偏移值表示从设备读取的所选位被保存并发送到主机的相对时钟周期。从PLD读取数据，每个读回时钟周期以一位的速率读取数据，并且从器件读取位读取回读时钟周期。当回读时钟周期的计数等于偏移量时，该位被选择并保存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式