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1. 发明申请

US20100122095A1 Hardware-facilitated secure software execution environment 失效
标题翻译：硬件安全软件执行环境
公开(公告)号：US20100122095A1
公开(公告)日：2010-05-13
申请号：US11707951
申请日：2007-02-20
申请人： Mark T. Jones , Peter M. Athanas , Cameron D. Patterson , Joshua N. Edmison , Anthony Mahar , Benjamin J. Muzal , Barry L. Polakowski , Jonathan P. Graf
发明人： Mark T. Jones , Peter M. Athanas , Cameron D. Patterson , Joshua N. Edmison , Anthony Mahar , Benjamin J. Muzal , Barry L. Polakowski , Jonathan P. Graf
IPC分类号： G06F21/22 , G06F12/14 , H04L9/28 , H04L9/14
CPC分类号： G06F21/53 , G06F21/72
摘要： A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.
摘要翻译：硬件便利的安全软件执行环境提供对程序指令和数据的保护，以防止未经授权的访问和/或执行，以在分发，外部存储器和执行期间保持软件或数据的机密性和完整性。安全计算环境通过使用基于硬件的安全方法和装置来提供防止软件隐私和篡改的保护来实现。哈佛架构CPU内核与加密管理单元（EMU）电路和安全密钥管理单元（SKU）电路一起在同一硅芯片上实例化。从一个或多个源获取的凭证信息由SKU电路组合以产生提供给EMU的一个或多个安全密钥，用于解密加密的程序指令和/或从非安全的片外来源获得的数据，例如作为外部RAM，信息存储设备或其他网络源。在非限制性说明性示例实现中，EMU根据由SKU提供的相应加密密钥对加密指令的单个存储器页面或数据进行解密。虽然在同一芯片上实例化，但是CPU内核不能直接访问SKU电路或者由SKU生成的加密密钥信息。

2. 发明授权

US07249010B1 Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA 有权
标题翻译：估计在FPGA中实现的设计对单事件不匹配的敏感性的方法
公开(公告)号：US07249010B1
公开(公告)日：2007-07-24
申请号：US10407280
申请日：2003-04-03
申请人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
发明人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F13/00 , G06F17/50 , G06F9/00 , G01R31/08 , G01F19/00 , G06F11/34 , G06F15/00 , G21C17/00 , H03K17/693 , H03K17/687
CPC分类号： G06F17/5054 , G06F2217/70
摘要： Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.
摘要翻译：估计在FPGA中实现的设计对单事件扰乱（SEU）的敏感性的方法。在FPGA中，许多配置存储单元可以响应于SEU而改变状态，而不影响在FPGA中实现的设计的功能。根据本发明的方法，确定“关心位”（与设计中实际使用的资源相关联的位）的数量。保留位的数量占FPGA中配置存储单元总数的比例决定了“SEU概率影响”（SEUPI）值。 “平均平均故障间隔时间”（MTBU）值是在FPGA中的一个配置存储器单元受SEU影响之前平均估计经过多少时间。为了获得FPGA中设计的“平均故障间隔时间”，MTBU值除以SEUPI值。

3. 发明授权

US07669168B1 Method and apparatus for dynamically connecting modules in a programmable device 有权
标题翻译：用于在可编程设备中动态连接模块的方法和装置
公开(公告)号：US07669168B1
公开(公告)日：2010-02-23
申请号：US11527963
申请日：2006-09-27
申请人： Cameron D. Patterson
发明人： Cameron D. Patterson
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for dynamically connecting modules within a programmable device is described. In an example, a programmable device is programmed with modular circuits. A bitstream is obtained from a database. The bitstream includes a first portion associated with a module and a second portion associated with an interface to the module. The bitstream is then modified with configuration data to connect the interface to one or more of the modular circuits. The programmable device is then configured using the modified bitstream.
摘要翻译：描述了在可编程设备内动态连接模块的方法和设备。在一个例子中，可编程器件用模块化电路编程。从数据库获得比特流。比特流包括与模块相关联的第一部分和与模块的接口相关联的第二部分。然后用配置数据修改比特流，以将该接口连接到一个或多个模块化电路。然后使用修改的比特流来配置可编程设备。

4. 发明授权

US06457164B1 Hetergeneous method for determining module placement in FPGAs 失效
标题翻译：用于确定FPGA中模块放置的Hetergeneous方法
公开(公告)号：US06457164B1
公开(公告)日：2002-09-24
申请号：US09608694
申请日：2000-06-29
申请人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
发明人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.
摘要翻译：本发明提供了在诸如FPGAS之类的可编程逻辑器件中使用的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。在设计时，SIMs实现自己，根据指定的参数对指定的FPGA进行定位。在一个实施例中，SIM引用或包括一个或多个楼层布置器，每个楼层布置器可以采用一个或多个布置算法。这样的放置算法可以包括例如：将数据路径逻辑按位地放置在规则线性模式中的线性排序算法; 在分布式RAM中实现网格图案中的存储器的矩形网格算法; 计数器和其他算术逻辑的柱状算法; 或用于诸如控制逻辑的随机逻辑的模拟退火算法。因此，包括多于一个SIM的设计可以利用相同或不同层级的多个放置算法。因此，整体设计可以利用不均匀的全球布局策略。

5. 发明授权

US06430732B1 Method for structured layout in a hardware description language 有权
标题翻译：硬件描述语言中结构化布局的方法
公开(公告)号：US06430732B1
公开(公告)日：2002-08-06
申请号：US09246253
申请日：1999-02-08
申请人： L. James Hwang , Cameron D. Patterson , Sujoy Mitra
发明人： L. James Hwang , Cameron D. Patterson , Sujoy Mitra
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method is provided for structured layout of design objects in a hardware description language (HDL). Standard features of the HDL are used to specify a first-level design object and the placement of other design objects in the first-level design object. A first-level design object is declared, wherein the first design object has no input or output ports and has one or more slots available for one or more second-level design objects. Values are assigned to attributes of the first-level design object to indicate placement for the second-level design objects within the first-level design object. The second-level design objects are declared as elements within the first-level design object, and the first- and second-level design objects are thereafter compiled.
摘要翻译：提供了一种用于硬件描述语言（HDL）中的设计对象的结构化布局的方法。 HDL的标准功能用于指定一级设计对象和其他设计对象在第一级设计对象中的放置。声明第一级设计对象，其中第一设计对象没有输入或输出端口，并且具有一个或多个可用于一个或多个二级设计对象的时隙。值被分配给第一级设计对象的属性，以指示第一级设计对象中的二级设计对象的放置。二级设计对象在第一级设计对象中被声明为元素，之后编译第一级和第二级设计对象。

6. 发明授权

US07143418B1 Core template package for creating run-time reconfigurable cores 有权
标题翻译：用于创建运行时可重构核心的核心模板包
公开(公告)号：US07143418B1
公开(公告)日：2006-11-28
申请号：US10013764
申请日：2001-12-10
申请人： Cameron D. Patterson
发明人： Cameron D. Patterson
IPC分类号： G06F9/00
CPC分类号： G06F17/5027 , G06F8/447
摘要： A method and apparatus for creating run-time reconfigurable cores using a core template package. The core template package provides an object-oriented application programming interface for specifying run-time reconfigurable (RTR) electronic circuit designs in a RTR application program. A run-time parameterizable (RTP) core library includes a plurality of predefined RTP core classes that implement selected functions in an electronic circuit design when invoked from an RTR application program. An RTP core template package includes a plurality of template classes. Each template class has a predefined set of method interfaces and fields. The RTP core template package further includes an RTP core template class that includes methods for building, connecting and traversing a hierarchy of RTP core objects based on the template classes and the predefined RTP core classes.
摘要翻译：一种用于使用核心模板包创建运行时可重构核心的方法和装置。核心模板包提供了一种面向对象的应用程序编程接口，用于在RTR应用程序中指定运行时可重配置（RTR）电子电路设计。运行时可参数化（RTP）核心库包括多个预定义的RTP核心类，其在从RTR应用程序调用时实现电子电路设计中的所选功能。 RTP核心模板包包括多个模板类。每个模板类都有一组预定义的方法接口和字段。 RTP核心模板包还包括RTP核心模板类，其包括基于模板类和预定义的RTP核心类构建，连接和遍历RTP核心对象的层次结构的方法。

7. 发明授权

US07080226B1 Field programmable gate array (FPGA) configuration data path for module communication 有权
标题翻译：用于模块通信的现场可编程门阵列（FPGA）配置数据通路
公开(公告)号：US07080226B1
公开(公告)日：2006-07-18
申请号：US10612522
申请日：2003-07-02
申请人： Cameron D. Patterson
发明人： Cameron D. Patterson
IPC分类号： G06F12/00
CPC分类号： H03K19/17748 , G06F12/1416 , H03K19/17736 , H03K19/1776
摘要： Data is transferred on a field programmable gate array (FPGA) by (1) retrieving a first set of data from a first block RAM column of a configuration memory of the FPGA, (2) storing the first set of data retrieved from the first block RAM column in a frame data output register, (3) transferring the first set of data from the frame data output register directly to a frame data input register through a configuration bus of the FPGA, and (4) transferring the first set of data from the frame data input register to a second block RAM column of the configuration memory. The configuration bus is wide (e.g., 32-bits), thereby resulting in a high data transfer bandwidth.
摘要翻译：数据通过（1）从FPGA的配置存储器的第一块RAM列获取第一组数据，（2）存储从第一块检索的第一组数据，在现场可编程门阵列（FPGA）上传送数据 RAM列，（3）通过FPGA的配置总线将第一组数据从帧数据输出寄存器直接传送到帧数据输入寄存器，（4）将第一组数据从帧数据输入寄存器到配置存储器的第二个块RAM列。配置总线宽（例如，32位），从而导致高数据传输带宽。

8. 发明授权

US08473754B2 Hardware-facilitated secure software execution environment 失效
标题翻译：硬件安全软件执行环境
公开(公告)号：US08473754B2
公开(公告)日：2013-06-25
申请号：US11707951
申请日：2007-02-20
申请人： Mark T. Jones , Peter M. Athanas , Cameron D. Patterson , Joshua N. Edmison , Anthony Mahar , Benjamin J. Muzal , Barry L. Polakowski , Jonathan P. Graf
发明人： Mark T. Jones , Peter M. Athanas , Cameron D. Patterson , Joshua N. Edmison , Anthony Mahar , Benjamin J. Muzal , Barry L. Polakowski , Jonathan P. Graf
IPC分类号： G06F11/30 , H04L9/32 , H04L9/00 , H04K1/00
CPC分类号： G06F21/53 , G06F21/72
摘要： A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.
摘要翻译：硬件便利的安全软件执行环境提供对程序指令和数据的保护，以防止未经授权的访问和/或执行，以在分发，外部存储器和执行期间保持软件或数据的机密性和完整性。安全计算环境通过使用基于硬件的安全方法和装置来提供防止软件隐私和篡改的保护来实现。哈佛架构CPU内核与加密管理单元（EMU）电路和安全密钥管理单元（SKU）电路一起在同一硅芯片上实例化。从一个或多个源获取的凭证信息由SKU电路组合以产生提供给EMU的一个或多个安全密钥，用于解密加密的程序指令和/或从非安全的片外来源获得的数据，例如作为外部RAM，信息存储设备或其他网络源。在非限制性说明性示例实现中，EMU根据由SKU提供的相应加密密钥对加密指令的单个存储器页面或数据进行解密。虽然在同一芯片上实例化，但是CPU内核不能直接访问SKU电路或者由SKU生成的加密密钥信息。

9. 发明授权

US07343578B1 Method and system for generating a bitstream view of a design 有权
标题翻译：用于生成设计的比特流视图的方法和系统
公开(公告)号：US07343578B1
公开(公告)日：2008-03-11
申请号：US10917064
申请日：2004-08-12
申请人： Cameron D. Patterson , Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan
发明人： Cameron D. Patterson , Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.
摘要翻译：公开了一种用于生成可编程逻辑器件（PLD）设计的位流视图的方法和系统。本发明允许物理电路描述（例如，PLD设计的基本配置位中的一个或多个）与逻辑电路描述（例如，构成PLD设计的一个或多个逻辑元件）的相关性，其中也可以被视为将PLD中设计实现的一个或多个物理元素与设计的一个或多个逻辑元素相关联。

10. 发明授权

US07139995B1 Integration of a run-time parameterizable core with a static circuit design 有权
标题翻译：集成一个运行时参数化的核心与静态电路设计
公开(公告)号：US07139995B1
公开(公告)日：2006-11-21
申请号：US10102585
申请日：2002-03-19
申请人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
发明人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054
摘要： Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.
摘要翻译：用于将运行时参数化逻辑核与静态电路设计集成的方法和装置。从硬件描述语言指定的主电路设计中生成配置比特流。主电路设计包括第一子电路设计，其指定RTP核心所需的PLD的所选资源子集以及RTP核心与主电路设计的其他部分之间的接口。通过执行运行时重新配置控制程序，将与第一子电路设计相对应的配置数据替换为实施RTP核心的配置数据。运行时重新配置程序然后使用更新的配置比特流配置PLD。

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