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1. 发明申请

US20070254394A1 Gallium nitride-based light emitting device having ESD protection capacity and method for manufacturing the same 失效
公开(公告)号：US20070254394A1
公开(公告)日：2007-11-01
申请号：US11812868
申请日：2007-06-22
申请人： Jun Seo , Suk Yoon , Seung Chae
发明人： Jun Seo , Suk Yoon , Seung Chae
IPC分类号： H01L21/00
CPC分类号： H01L33/04 , H01L27/0248 , H01L27/15 , H01L33/32 , H01L33/38 , H01L33/44 , H01L2933/0016
摘要： A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed on one region of the n-type GaN-based clad layer, and two or more MIM type tunnel junctions formed on the other regions of the n-type GaN-based clad layer. Each of the MIM type tunnel junctions comprises a lower metal layer formed on the GaN-based clad layer so as to contact the n-type GaN-based clad layer, an insulating film formed on the lower metal layer, and an upper metal layer formed on the insulating film. The device is protected from reverse ESD voltage, so that tolerance to reverse ESD voltage can be enhanced, thereby improving reliability of the device.

2. 发明申请

US20060157718A1 Gallium nitride-based light emitting device having ESD protection capacity and method for manufacturing the same 有权
标题翻译：具有ESD保护能力的氮化镓系发光器件及其制造方法
公开(公告)号：US20060157718A1
公开(公告)日：2006-07-20
申请号：US11220844
申请日：2005-09-08
申请人： Jun Seo , Suk Yoon , Seung Chae
发明人： Jun Seo , Suk Yoon , Seung Chae
IPC分类号： H01L31/12 , H01L27/15
CPC分类号： H01L33/04 , H01L27/0248 , H01L27/15 , H01L33/32 , H01L33/38 , H01L33/44 , H01L2933/0016
摘要： A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed on one region of the n-type GaN-based clad layer, and two or more MIM type tunnel junctions formed on the other regions of the n-type GaN-based clad layer. Each of the MIM type tunnel junctions comprises a lower metal layer formed on the GaN-based clad layer so as to contact the n-type GaN-based clad layer, an insulating film formed on the lower metal layer, and an upper metal layer formed on the insulating film. The device is protected from reverse ESD voltage, so that tolerance to reverse ESD voltage can be enhanced, thereby improving reliability of the device.
摘要翻译：公开了一种氮化镓基发光器件及其制造方法。发光器件包括依次层叠在衬底上的n型GaN基覆盖层，有源层，p型GaN基覆盖层和p侧电极。该器件还包括形成在n型GaN基覆盖层的一个区域上的n侧电极和形成在n型GaN基覆盖层的其它区域上的两个或更多个MIM型隧道结。每个MIM型隧道结包括形成在GaN基覆层上的下金属层，以便接触n型GaN基覆层，形成在下金属层上的绝缘膜和形成的上金属层在绝缘膜上。该器件可防止反向ESD电压，从而可以提高对反向ESD电压的容限，从而提高器件的可靠性。

3. 发明申请

US20060033116A1 Gallium nitride based semiconductor light emitting diode and process for preparing the same 审中-公开
标题翻译：氮化镓基半导体发光二极管及其制备方法
公开(公告)号：US20060033116A1
公开(公告)日：2006-02-16
申请号：US11049876
申请日：2005-02-04
申请人： Seung Chae , Jun Kwak , Hyoun Shin , Jun Seo
发明人： Seung Chae , Jun Kwak , Hyoun Shin , Jun Seo
IPC分类号： H01L29/221
CPC分类号： H01L21/28575 , H01L29/452 , H01L33/32 , H01L33/40 , H01L33/42 , H01L2924/10155
摘要： The present invention provides a gallium nitride based semiconductor light emitting diode having high transparency, and at the same time, capable of improving contact resistance between a p-type GaN layer and electrode and a process for preparing the same. These objects can be accomplished by forming, on an upper part of a upper clad layer made of p-GaN, an ohmic contact forming layer using MIO, ZIO and CIO (In2O3 including one of Mg, Zn and Cu), and then a transparent electrode layer and a second electrode with ITO thereon, so as to improve contact resistance between the upper clad layer and the second electrode while providing high transparency.
摘要翻译：本发明提供一种具有高透明度，同时可提高p型GaN层与电极之间的接触电阻的氮化镓系半导体发光二极管及其制备方法。这些目的可以通过在由p-GaN制成的上覆盖层的上部上形成使用MIO，ZIO和CIO的欧姆接触形成层来实现的（In 2 N 3 O 3， / SUB>包括Mg，Zn和Cu中的一种），然后是透明电极层和具有ITO的第二电极，以提高上覆层和第二电极之间的接触电阻，同时提供高透明度。

4. 发明授权

US08270211B2 Electromechanical switch and method of forming the same 有权
标题翻译：机电开关及其形成方法
公开(公告)号：US08270211B2
公开(公告)日：2012-09-18
申请号：US13082605
申请日：2011-04-08
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
IPC分类号： G11C11/50
CPC分类号： H01L28/40 , H01L27/10894
摘要： A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储装置包括存储节点，第一电极和形成在存储单元中的第二电极，所述存储节点存储电荷，所述第一电极包括电连接到第二部分的第一部分，所述第一部分移动以连接到当第二电极通电时的存储节点。

5. 发明申请

US20110006353A1 DRAM DEVICES 审中-公开
标题翻译： DRAM设备
公开(公告)号：US20110006353A1
公开(公告)日：2011-01-13
申请号：US12830788
申请日：2010-07-06
申请人： Min-Sang KIM , Dong-Won Kim , Jun Seo , Keun-Hwi Cho , Hyun-Jun Bae , Ji-Myoung Lee
发明人： Min-Sang KIM , Dong-Won Kim , Jun Seo , Keun-Hwi Cho , Hyun-Jun Bae , Ji-Myoung Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L28/60
摘要： A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the plug, and at least one word line under the conductive plate and spaced apart from the conductive plate. The DRAM device further includes at least one first conductive pad under the conductive plate, the at least one first conductive pad being spaced apart from the conductive plate in a first state and being electrically connected to the conductive plate in a second state, the at least one first conductive pad being disposed between the plug and an adjacent word line of the at least one word line, and the at least one first conductive pad being electrically connected to a respective capacitor of the at least one capacitor.
摘要翻译： DRAM装置包括在基板上的插头，电连接到插头并与衬底重叠的导电板，基板上的至少一个电容器和与插头间隔开的至少一个电容器，以及导电板下面的至少一个字线并间隔开从导电板。 DRAM器件还包括在导电板下方的至少一个第一导电焊盘，所述至少一个第一导电焊盘在第一状态下与导电板间隔开并且在第二状态下电连接到导电板，至少一个第一导电焊盘设置在所述插头和所述至少一个字线的相邻字线之间，并且所述至少一个第一导电焊盘电连接到所述至少一个电容器的相应电容器。

6. 发明授权

US07655976B2 Field effect transistors having protruded active regions and methods of fabricating such transistors 有权
标题翻译：具有突出的有源区的场效应晶体管和制造这种晶体管的方法
公开(公告)号：US07655976B2
公开(公告)日：2010-02-02
申请号：US12170537
申请日：2008-07-10
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

7. 发明授权

US07531449B2 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US07531449B2
公开(公告)日：2009-05-12
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

8. 发明申请

US20050191813A1 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US20050191813A1
公开(公告)日：2005-09-01
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

9. 发明授权

US06784097B2 Method of manufacturing a semiconductor device with a self-aligned contact 有权
标题翻译：制造具有自对准接触的半导体器件的方法
公开(公告)号：US06784097B2
公开(公告)日：2004-08-31
申请号：US10410340
申请日：2003-04-10
申请人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
发明人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a self-aligned contact includes providing a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region, forming a first insulating layer on the semiconductor substrate, forming a plurality of conductive patterns on the first insulating layer, forming sequentially second, third and fourth insulating layers over the entire surface of the semiconductor substrate, etching the fourth insulating layer to form spacers on sidewalls of the conductive patterns, forming sequentially fifth and sixth insulating layers over the entire surface of the semiconductor substrate; and etching the sixth insulating layer using a portion of the fifth insulating layer over the self-aligned contact region as an etch stopper, and etching the fifth insulating lever to form a self-aligned contact.
摘要翻译：具有自对准接触的半导体器件的制造方法包括提供具有自对准接触区域和非自对准接触区域的半导体衬底，在半导体衬底上形成第一绝缘层，形成多个导电在第一绝缘层上形成图案，在半导体衬底的整个表面上依次形成第二绝缘层，第三绝缘层和第四绝缘层，蚀刻第四绝缘层，以在导电图案的侧壁上形成间隔物，在整个表面上依次形成第五和第六绝缘层半导体衬底的表面; 以及使用所述第五绝缘层的一部分在所述自对准接触区域上作为蚀刻停止层蚀刻所述第六绝缘层，并且蚀刻所述第五绝缘杆以形成自对准接触。

10. 发明授权

US06573602B2 Semiconductor device with a self-aligned contact and a method of manufacturing the same 有权
公开(公告)号：US06573602B2
公开(公告)日：2003-06-03
申请号：US10193091
申请日：2002-07-12
申请人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
发明人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
IPC分类号： H01L2302
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

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