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1. 发明申请

US20090068809A1 SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL ETCH STOPPER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有本地止动器的半导体存储器件及其制造方法
公开(公告)号：US20090068809A1
公开(公告)日：2009-03-12
申请号：US12267785
申请日：2008-11-10
申请人： Jung-woo SEO , Jong-seo HONG , Tae-hyuk AHN , Jeong-sic JEON , Jun-sik HONG , Young-sun CHO
发明人： Jung-woo SEO , Jong-seo HONG , Tae-hyuk AHN , Jeong-sic JEON , Jun-sik HONG , Young-sun CHO
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

2. 发明申请

US20080096347A1 METHODS OF FORMING ELECTRONIC DEVICES INCLUDING ELECTRODES WITH INSULATING SPACERS THEREON 失效
标题翻译：形成包含绝缘间隔电极的电子器件的方法
公开(公告)号：US20080096347A1
公开(公告)日：2008-04-24
申请号：US11956360
申请日：2007-12-14
申请人： In-joon Yeo , Tae-hyuk Ahn , Kwang-wook Lee , Jung-woo Seo , Jeong-sic Jeon
发明人： In-joon Yeo , Tae-hyuk Ahn , Kwang-wook Lee , Jung-woo Seo , Jeong-sic Jeon
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.
摘要翻译：电子器件可以包括衬底，衬底上的导电层和绝缘间隔物。导电电极可以具有远离衬底延伸的电极壁。绝缘间隔物可以设置在电极壁上，电极壁的部分在衬底和绝缘间隔物之间没有绝缘间隔物，并且电极最远离衬底的部分可以没有绝缘间隔物。还讨论了相关的方法和结构。

3. 发明授权

US07132708B2 Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
标题翻译：具有自对准触点的半导体存储器件及其制造方法
公开(公告)号：US07132708B2
公开(公告)日：2006-11-07
申请号：US11054593
申请日：2005-02-09
申请人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
发明人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10814 , H01L27/10888
摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.
摘要翻译：一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准与第二和第一间隔物。

4. 发明授权

US07053435B2 Electronic devices including electrodes with insulating spacers thereon 失效
标题翻译：电子设备包括其上具有绝缘隔离物的电极
公开(公告)号：US07053435B2
公开(公告)日：2006-05-30
申请号：US10796931
申请日：2004-03-10
申请人： In-joon Yeo , Tae-hyuk Ahn , Kwang-wook Lee , Jung-woo Seo , Jeong-sic Jeon
发明人： In-joon Yeo , Tae-hyuk Ahn , Kwang-wook Lee , Jung-woo Seo , Jeong-sic Jeon
IPC分类号： H01L21/20
CPC分类号： H01L28/90 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.
摘要翻译：电子器件可以包括衬底，衬底上的导电层和绝缘间隔物。导电电极可以具有远离衬底延伸的电极壁。绝缘间隔物可以设置在电极壁上，电极壁的部分在衬底和绝缘间隔物之间没有绝缘隔离物。还讨论了相关的方法和结构。

5. 发明授权

US06927127B2 Method of manufacturing a semiconductor memory device 失效
公开(公告)号：US06927127B2
公开(公告)日：2005-08-09
申请号：US10954835
申请日：2004-09-29
申请人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
发明人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/76831 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

6. 发明申请

US20050093046A1 Plurality of capacitors employing holding layer patterns and method of fabricating the same 审中-公开
标题翻译：采用保持层图案的多种电容器及其制造方法
公开(公告)号：US20050093046A1
公开(公告)日：2005-05-05
申请号：US10971022
申请日：2004-10-25
申请人： Tae-Hyuk Ahn
发明人： Tae-Hyuk Ahn
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/02 , H01L27/108 , G02F1/1347 , H01L29/94
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10852 , Y10T29/42 , Y10T29/435 , Y10T29/49117 , Y10T29/49124
摘要： A plurality of capacitors employing holding layer patterns, and a method of fabricating the same, the plurality of capacitors including a plurality of cylinder-shaped lower plates repeatedly aligned in two dimensions. Holding layer patterns are located between the uppermost portions and the lowermost portions of the plurality of lower plates, and connect the adjacent side walls of the plurality of lower plates. An upper plate fills the spaces inside the plurality of lower plates and the spaces between the side walls of the plurality of lower plates. A capacitor dielectric layer is interposed between the plurality of lower plates and the upper plate, and insulates the lower plates and the upper plate.
摘要翻译：使用保持层图案的多个电容器及其制造方法，所述多个电容器包括在二维上重复排列的多个圆筒形下板。保持层图案位于多个下板的最上部和最下部之间，并且连接多个下板的相邻侧壁。上板填充多个下板中的空间和多个下板的侧壁之间的空间。在多个下板和上板之间插入电容器电介质层，并使下板和上板绝缘。

7. 发明授权

US06784097B2 Method of manufacturing a semiconductor device with a self-aligned contact 有权
标题翻译：制造具有自对准接触的半导体器件的方法
公开(公告)号：US06784097B2
公开(公告)日：2004-08-31
申请号：US10410340
申请日：2003-04-10
申请人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
发明人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a self-aligned contact includes providing a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region, forming a first insulating layer on the semiconductor substrate, forming a plurality of conductive patterns on the first insulating layer, forming sequentially second, third and fourth insulating layers over the entire surface of the semiconductor substrate, etching the fourth insulating layer to form spacers on sidewalls of the conductive patterns, forming sequentially fifth and sixth insulating layers over the entire surface of the semiconductor substrate; and etching the sixth insulating layer using a portion of the fifth insulating layer over the self-aligned contact region as an etch stopper, and etching the fifth insulating lever to form a self-aligned contact.
摘要翻译：具有自对准接触的半导体器件的制造方法包括提供具有自对准接触区域和非自对准接触区域的半导体衬底，在半导体衬底上形成第一绝缘层，形成多个导电在第一绝缘层上形成图案，在半导体衬底的整个表面上依次形成第二绝缘层，第三绝缘层和第四绝缘层，蚀刻第四绝缘层，以在导电图案的侧壁上形成间隔物，在整个表面上依次形成第五和第六绝缘层半导体衬底的表面; 以及使用所述第五绝缘层的一部分在所述自对准接触区域上作为蚀刻停止层蚀刻所述第六绝缘层，并且蚀刻所述第五绝缘杆以形成自对准接触。

8. 发明授权

US06719808B1 Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask 失效
标题翻译：使用多晶硅硬掩模制造半导体器件的方法和装置
公开(公告)号：US06719808B1
公开(公告)日：2004-04-13
申请号：US09695068
申请日：2000-10-25
申请人： Ji-soo Kim , Tae-hyuk Ahn , Won-seok Lee , Wan-jae Park
发明人： Ji-soo Kim , Tae-hyuk Ahn , Won-seok Lee , Wan-jae Park
IPC分类号： H01L21302
CPC分类号： H01L21/32137 , H01L21/31144
摘要： A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate. The processing apparatus includes a reaction chamber including a spin chuck which supports the semiconductor substrate for rotation, a gas supply unit for supplying a process gas to the reaction chamber, a gas injection unit for injecting the process gas supplied by the gas supply unit into the reaction chamber in a direction parallel to the major surface of the semiconductor substrate, and an exhaust unit for exhausting gases from the reaction chamber.
摘要翻译：用于制造半导体器件的方法和装置剥离多晶硅硬掩模，而不会损坏通过使用多晶硅硬掩模形成的开口暴露的层作为蚀刻掩模。该方法包括在第一层上形成图案中的多晶硅硬掩模以暴露第一层的一部分，使用多晶硅硬掩模作为蚀刻掩模干蚀刻第一层的暴露部分，以在第一层中形成开口然后通过在多晶硅硬掩模上沿着与半导体基板的主表面平行的方向提供蚀刻气体来除去多晶硅硬掩模。处理装置包括：反应室，包括支撑旋转用半导体基板的旋转卡盘，向反应室供给处理气体的气体供给单元，将由气体供给单元供给的处理气体注入到反应室在与半导体基板的主表面平行的方向上，以及用于从反应室排出气体的排气单元。

9. 发明授权

US06573602B2 Semiconductor device with a self-aligned contact and a method of manufacturing the same 有权
公开(公告)号：US06573602B2
公开(公告)日：2003-06-03
申请号：US10193091
申请日：2002-07-12
申请人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
发明人： Jun Seo , Tae-Hyuk Ahn , Myeong-Cheol Kim
IPC分类号： H01L2302
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a self-aligned contact and a method for forming the same, including a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region; a first insulating layer formed on the semiconductor substrate that exposes the self-aligned contact; conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the non-self-aligned contact region and on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.

10. 发明授权

US06573551B1 Semiconductor memory device having self-aligned contact and fabricating method thereof 有权
公开(公告)号：US06573551B1
公开(公告)日：2003-06-03
申请号：US09654664
申请日：2000-09-05
申请人： Myeong-cheol Kim , Byeong-yun Nam , Sang-sup Jeong , Tae-hyuk Ahn
发明人： Myeong-cheol Kim , Byeong-yun Nam , Sang-sup Jeong , Tae-hyuk Ahn
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant structure having the bit lines and removing the insulating layer on the bit lines and on the first interlayer dielectric film to form insulating spacers only at both side walls of the bit lines, forming a second interlayer dielectric film on the resultant structure having the insulating spacers and forming a fourth opening self-aligned to the insulating spacers to open the surface of the second pad layer, and filling the fourth opening with a conductive material.

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