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1. 发明授权

US07524733B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 有权
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07524733B2
公开(公告)日：2009-04-28
申请号：US11735919
申请日：2007-04-16
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

2. 发明申请

US20050191813A1 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US20050191813A1
公开(公告)日：2005-09-01
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

3. 发明授权

US07221023B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07221023B2
公开(公告)日：2007-05-22
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

4. 发明授权

US07833864B2 Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate 有权
标题翻译：掺杂多晶硅层的方法，其利用栅极绝缘层以防止离子注入的杂质扩散到下面的半导体衬底中
公开(公告)号：US07833864B2
公开(公告)日：2010-11-16
申请号：US11738620
申请日：2007-04-23
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

5. 发明授权

US07223649B2 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US07223649B2
公开(公告)日：2007-05-29
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

6. 发明授权

US07259069B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US07259069B2
公开(公告)日：2007-08-21
申请号：US11229202
申请日：2005-09-15
申请人： Nak-Jin Son , Ji-Young Kim
发明人： Nak-Jin Son , Ji-Young Kim
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/331
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/1041 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/66537 , H01L29/66553 , H01L29/78
摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

7. 发明申请

US20060008994A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060008994A1
公开(公告)日：2006-01-12
申请号：US11229202
申请日：2005-09-15
申请人： Nak-Jin Son , Ji-Young Kim
发明人： Nak-Jin Son , Ji-Young Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/1041 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/66537 , H01L29/66553 , H01L29/78
摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.
摘要翻译：公开了一种半导体器件及其制造方法。在半导体衬底的有源区中形成沟槽。掺杂层形成在沟槽的内壁上。沟槽填充有第一半导体层。在第一半导体层和基板上形成栅极绝缘层。在栅极绝缘层上形成两个栅电极，使得沟槽位于两个栅电极之间。在每个栅电极的两侧的基板中形成第一和第二杂质区。由于掺杂层局部地形成在沟槽区域中，源极和漏极区域与重掺杂层完全分离，以削弱PN结的电场，从而改善了源极和漏极之间的刷新并防止穿透。

8. 发明授权

US07268043B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07268043B2
公开(公告)日：2007-09-11
申请号：US11565127
申请日：2006-11-30
申请人： Nak-Jin Son , Ji-Young Kim
发明人： Nak-Jin Son , Ji-Young Kim
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/331
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/1041 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/66537 , H01L29/66553 , H01L29/78
摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.
摘要翻译：公开了一种半导体器件及其制造方法。在半导体衬底的有源区中形成沟槽。掺杂层形成在沟槽的内壁上。沟槽填充有第一半导体层。在第一半导体层和基板上形成栅极绝缘层。在栅极绝缘层上形成两个栅电极，使得沟槽位于两个栅电极之间。在每个栅电极的两侧的基板中形成第一和第二杂质区。由于掺杂层局部地形成在沟槽区域中，源极和漏极区域与重掺杂层完全分离，以削弱PN结的电场，从而改善了源极和漏极之间的刷新并防止穿透。

9. 发明授权

US07009255B2 Semiconductor device having punch-through structure off-setting the edge of the gate electrodes 有权
标题翻译：具有穿通结构的半导体器件使栅电极的边缘脱离
公开(公告)号：US07009255B2
公开(公告)日：2006-03-07
申请号：US10445109
申请日：2003-05-23
申请人： Nak-Jin Son , Ji-Young Kim
发明人： Nak-Jin Son , Ji-Young Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/1041 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/66537 , H01L29/66553 , H01L29/78
摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.
摘要翻译：公开了一种半导体器件及其制造方法。在半导体衬底的有源区中形成沟槽。掺杂层形成在沟槽的内壁上。沟槽填充有第一半导体层。在第一半导体层和基板上形成栅极绝缘层。在栅极绝缘层上形成两个栅电极，使得沟槽位于两个栅电极之间。在每个栅电极的两侧的基板中形成第一和第二杂质区。由于掺杂层局部地形成在沟槽区域中，源极和漏极区域与重掺杂层完全分离，以削弱PN结的电场，从而改善了源极和漏极之间的刷新并防止穿透。

10. 发明申请

US20050042832A1 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US20050042832A1
公开(公告)日：2005-02-24
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L29/51 , H01L21/3205 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

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