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1. 发明授权

US07524733B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 有权
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07524733B2
公开(公告)日：2009-04-28
申请号：US11735919
申请日：2007-04-16
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

2. 发明授权

US07221023B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07221023B2
公开(公告)日：2007-05-22
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

3. 发明申请

US20050191813A1 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US20050191813A1
公开(公告)日：2005-09-01
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

4. 发明授权

US07696570B2 Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
标题翻译：在通道部分孔中具有沟道区的半导体器件的晶体管及其形成方法
公开(公告)号：US07696570B2
公开(公告)日：2010-04-13
申请号：US12350708
申请日：2009-01-08
申请人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/1087
摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
摘要翻译：根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。防止对应于源区和漏区的电极杂质区之间的穿透。

5. 发明申请

US20050208715A1 Method of fabricating fin field effect transistor using isotropic etching technique 有权
标题翻译：使用各向同性蚀刻技术制造散射场效应晶体管的方法
公开(公告)号：US20050208715A1
公开(公告)日：2005-09-22
申请号：US11083660
申请日：2005-03-16
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/7851 , H01L29/66818
摘要： Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.
摘要翻译：公开了制造鳍式场效应晶体管（FinFET）的方法。本发明的实施例提供了通过优化用于形成翅片的方法来制造FinFET的方法，使得防止短通道效应并实现高集成度。因此，可以容易地形成使用当前的光刻蚀刻技术难以形成的翅片。

6. 发明申请

US20050179030A1 Field effect transistor device with channel fin structure and method of fabricating the same 失效
标题翻译：具有通道鳍结构的场效应晶体管器件及其制造方法
公开(公告)号：US20050179030A1
公开(公告)日：2005-08-18
申请号：US10938436
申请日：2004-09-09
申请人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
发明人： Hyeoung-Won Seo , Woun-Suck Yang , Du-Heon Song , Jae-Man Yoon
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795
摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.
摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。栅极线形成为覆盖并延伸穿过通道散热片。源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。描述和要求保护其他实施例。

7. 发明申请

US20050218434A1 Transistor having asymmetric channel region, semiconductor device including the same, and method of fabricating semiconductor device including the same 有权
标题翻译：具有不对称沟道区的晶体管，包括该晶体管的半导体器件及其制造方法
公开(公告)号：US20050218434A1
公开(公告)日：2005-10-06
申请号：US11100685
申请日：2005-04-06
申请人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10873 , H01L27/10876 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.
摘要翻译：根据本发明的实施例，晶体管包括具有有源区的半导体衬底。通道槽被设置成穿过有源区域。栅极绝缘层覆盖沟道沟槽的内壁。设置栅极图案以填充沟道沟槽并在半导体衬底的主表面上延伸。具有第一导电性的源极/漏极区域设置在沟道沟槽的两侧的有源区域中。在源极/漏极区之一下方设置具有第二导电性的沟道杂质区，以与沟道沟槽的至少一个侧壁接触。

8. 发明申请

US20050173744A1 Recessed-type field effect transistor with reduced body effect 审中-公开
标题翻译：嵌入式场效应晶体管具有降低的体效
公开(公告)号：US20050173744A1
公开(公告)日：2005-08-11
申请号：US11051834
申请日：2005-02-04
申请人： Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee , Hyeoung-Won Seo , Dae-Joong Won
发明人： Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee , Hyeoung-Won Seo , Dae-Joong Won
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L29/10 , H01L29/423 , H01L29/94
CPC分类号： H01L29/66537 , H01L21/823437 , H01L21/823487 , H01L27/10852 , H01L27/10876 , H01L29/1041 , H01L29/42376 , H01L29/66621
摘要： For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.
摘要翻译：为了制造场效应晶体管，在半导体衬底的表面的下方形成了掺杂杂质的沟道区。在半导体衬底中形成开口，形成超掺杂沟道区。在开口的壁处形成栅极绝缘体，使得超掺杂沟道区在开口的底部邻接栅极绝缘体。开口填充有栅电极。这种超掺杂沟道区域防止场效应晶体管中的不期望的体效应。

9. 发明授权

US07534708B2 Recessed-type field effect transistor with reduced body effect 有权
标题翻译：嵌入式场效应晶体管具有降低的体效
公开(公告)号：US07534708B2
公开(公告)日：2009-05-19
申请号：US11452867
申请日：2006-06-14
申请人： Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee , Hyeoung-Won Seo , Dae-Joong Won
发明人： Dong-Hyun Kim , Du-Heon Song , Sang-Hyun Lee , Hyeoung-Won Seo , Dae-Joong Won
IPC分类号： H01L21/3205
CPC分类号： H01L29/66537 , H01L21/823437 , H01L21/823487 , H01L27/10852 , H01L27/10876 , H01L29/1041 , H01L29/42376 , H01L29/66621
摘要： For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.
摘要翻译：为了制造场效应晶体管，在半导体衬底的表面的下方形成了掺杂杂质的沟道区。在半导体衬底中形成开口，形成超掺杂沟道区。在开口的壁处形成栅极绝缘体，使得超掺杂沟道区在开口的底部邻接栅极绝缘体。开口填充有栅电极。这种超掺杂沟道区域防止场效应晶体管中的不期望的体效应。

10. 发明授权

US07491603B2 Transistors of semiconductor device having channel region in a channel-portion hole and methods of forming the same 有权
标题翻译：在通道部孔中具有沟道区的半导体器件的晶体管及其形成方法
公开(公告)号：US07491603B2
公开(公告)日：2009-02-17
申请号：US11073246
申请日：2005-03-04
申请人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sang-Hyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/1087
摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
摘要翻译：根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。防止对应于源区和漏区的电极杂质区之间的穿透。

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