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1. 发明申请

US20080113511A1 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US20080113511A1
公开(公告)日：2008-05-15
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

2. 发明授权

US07531449B2 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US07531449B2
公开(公告)日：2009-05-12
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

3. 发明申请

US20080146002A1 Method of manufacturing semiconductor device having buried gate 有权
标题翻译：制造具有掩埋栅极的半导体器件的方法
公开(公告)号：US20080146002A1
公开(公告)日：2008-06-19
申请号：US12000496
申请日：2007-12-13
申请人： Eun-young Kang , Jun Seo , Jae-seung Hwang , Sung-il Cho , Yong-hyun Kwon
发明人： Eun-young Kang , Jun Seo , Jae-seung Hwang , Sung-il Cho , Yong-hyun Kwon
IPC分类号： H01L21/76
CPC分类号： H01L21/823456 , H01L21/823481 , H01L27/105 , H01L27/1052
摘要： A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.
摘要翻译：制造具有掩埋栅极的半导体器件的方法可以包括形成具有相等宽度的顺序层叠的第一掩模图案和第二掩模图案的叠层结构，以暴露半导体衬底的有源区和隔离区。在通过仅减小第一掩模图案的宽度来形成减小的第一掩模图案之后，可以通过使用第二掩模图案作为蚀刻掩模蚀刻半导体衬底的暴露部分来在有源区域和隔离区域中形成沟槽。然后，栅极绝缘膜可以形成在有源区域中的沟槽的内壁上，并且导电材料可以被埋入有源区域和隔离区域中的沟槽中，以形成栅极。

4. 发明授权

US07723191B2 Method of manufacturing semiconductor device having buried gate 有权
标题翻译：制造具有掩埋栅极的半导体器件的方法
公开(公告)号：US07723191B2
公开(公告)日：2010-05-25
申请号：US12000496
申请日：2007-12-13
申请人： Eun-young Kang , Jun Seo , Jae-seung Hwang , Sung-il Cho , Yong-hyun Kwon
发明人： Eun-young Kang , Jun Seo , Jae-seung Hwang , Sung-il Cho , Yong-hyun Kwon
IPC分类号： H01L21/336
CPC分类号： H01L21/823456 , H01L21/823481 , H01L27/105 , H01L27/1052
摘要： A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.
摘要翻译：制造具有掩埋栅极的半导体器件的方法可以包括形成具有相等宽度的顺序层叠的第一掩模图案和第二掩模图案的叠层结构，以暴露半导体衬底的有源区和隔离区。在通过仅减小第一掩模图案的宽度来形成减小的第一掩模图案之后，可以通过使用第二掩模图案作为蚀刻掩模蚀刻半导体衬底的暴露部分来在有源区域和隔离区域中形成沟槽。然后，栅极绝缘膜可以形成在有源区域中的沟槽的内壁上，并且导电材料可以被埋入有源区域和隔离区域中的沟槽中以形成栅极。

5. 发明授权

US07749902B2 Methods of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07749902B2
公开(公告)日：2010-07-06
申请号：US11825272
申请日：2007-06-05
申请人： Hyun-chul Kim , Sung-il Cho , Jae-seung Hwang , Jun Sen , Yong-hyun Kwon
发明人： Hyun-chul Kim , Sung-il Cho , Jae-seung Hwang , Jun Sen , Yong-hyun Kwon
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , Y10S438/942 , Y10S438/946 , Y10S438/947
摘要： Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.
摘要翻译：提供了使用双重图案化制造半导体器件的方法。该方法包括：在物体层上形成具有沿第一方向的凹陷的第一材料层图案和形成在第一材料层图案上的第二材料层图案; 在与第一方向垂直的方向上选择性蚀刻第二材料层图案和第一材料层图案以形成蚀刻掩模; 并蚀刻目标层以形成微小的图案。

6. 发明申请

US20080194108A1 Methods of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080194108A1
公开(公告)日：2008-08-14
申请号：US11825272
申请日：2007-06-05
申请人： Hyun-chul Kim , Sung-il Cho , Jae-seung Hwang , Jun Sen , Yong-hyun Kwon
发明人： Hyun-chul Kim , Sung-il Cho , Jae-seung Hwang , Jun Sen , Yong-hyun Kwon
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , Y10S438/942 , Y10S438/946 , Y10S438/947
摘要： Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.
摘要翻译：提供了使用双重图案化制造半导体器件的方法。该方法包括：在物体层上形成具有沿第一方向的凹陷的第一材料层图案和形成在第一材料层图案上的第二材料层图案; 在与第一方向垂直的方向上选择性蚀刻第二材料层图案和第一材料层图案以形成蚀刻掩模; 并蚀刻目标层以形成微小的图案。

7. 发明授权

US07402488B2 Method of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07402488B2
公开(公告)日：2008-07-22
申请号：US11159130
申请日：2005-06-23
申请人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
发明人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L27/10852 , H01L28/91
摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.
摘要翻译：半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案，蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层，所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

8. 发明申请

US20050287738A1 Method of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050287738A1
公开(公告)日：2005-12-29
申请号：US11159130
申请日：2005-06-23
申请人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
发明人： Sung-il Cho , Kyeong-koo Chi , Seung-pil Chung , Chang-jin Kang , Cheol-kyu Lee
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L27/10852 , H01L28/91
摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.
摘要翻译：半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案，蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层，所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

9. 发明授权

US06198468B1 Apparatus for performing various on-screen display functions and methods for each function 失效
标题翻译：用于执行各种屏幕显示功能的装置和用于每个功能的方法
公开(公告)号：US06198468B1
公开(公告)日：2001-03-06
申请号：US08969101
申请日：1997-11-13
申请人： Sung-il Cho
发明人： Sung-il Cho
IPC分类号： G06F104
CPC分类号： H04N5/44504 , H04N9/64 , H04N21/431 , Y10S248/917
摘要： An apparatus having various on-screen display (OSD) functions and methods for each function are provided. The apparatus includes an on-screen display device for receiving serial data having a RAM write address, a ROM address, and the on-screen display functions. The apparatus synthesizes a character signal corresponding to serial data with a background color signal or an external composite video signal in response to an internal or external composite synchronous signal and provides the result to a monitor. The apparatus also includes a synchronous signal generating device for generating internal horizontal and vertical synchronous signals upon receiving a main clock signal, synthesizing means for synthesizing an internal equalization pulse with the internal horizontal and vertical synchronous signals, and means for determining the internal composite synchronous signal or the external composite synchronous signal extracted from the composite video signal. A control device is also part of the OSD apparatus. The control device outputs user serial data to the on-screen display device, generates the main clock signal from a system clock, and controls the on-screen display device and the synchronous signal generating device.
摘要翻译：提供具有各种屏幕显示（OSD）功能和各种功能的方法的设备。该装置包括用于接收具有RAM写地址，ROM地址和屏幕显示功能的串行数据的屏幕显示装置。该装置响应于内部或外部复合同步信号，合成具有背景颜色信号或外部复合视频信号的与串行数据对应的字符信号，并将结果提供给监视器。该装置还包括同步信号发生装置，用于在接收主时钟信号时产生内部水平和垂直同步信号，合成装置用于将内部均衡脉冲与内部水平和垂直同步信号合成，以及用于确定内部复合同步信号的装置或从复合视频信号中提取的外部复合同步信号。控制装置也是OSD装置的一部分。控制装置将用户串行数据输出到屏幕显示装置，从系统时钟产生主时钟信号，并控制屏幕显示装置和同步信号产生装置。

10. 发明授权

US5398270A Data coincidence detecting circuit 失效
标题翻译：数据一致检测电路
公开(公告)号：US5398270A
公开(公告)日：1995-03-14
申请号：US29597
申请日：1993-03-11
申请人： Sung-il Cho , Ki-ho Shin
发明人： Sung-il Cho , Ki-ho Shin
IPC分类号： G06F7/04 , G06F7/02 , G06F11/00 , H03K3/037 , H03K5/19 , H03K19/21 , H03K23/66 , H03L7/00 , H03K21/08
CPC分类号： G06F7/02 , H03K19/21 , H03K23/66 , H03K3/037
摘要： A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.
摘要翻译：一种数据符合检测电路，包括用于接收n位数据的寄存器，用于向上计数直到2n以比较n位数据的计数器，比较器，用于将寄存器的输出和计数器的输出分别对应于产生符合检测信号，连接到比较器的输出的掩模部分，用于掩蔽从输入n位数据的时间点到数据输入结束的时间点的周期;以及逻辑电路，用于逻辑地加法屏蔽部分的输出和比较器的输出以输出结果。

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