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1. 发明授权

US6011412A Frequency shift detection circuit with selectable granularity 失效
标题翻译：具有可选粒度的频移检测电路
公开(公告)号：US6011412A
公开(公告)日：2000-01-04
申请号：US70925
申请日：1998-05-01
申请人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
发明人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
IPC分类号： H03D13/00
CPC分类号： H03D13/004
摘要： A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica. By selecting or tapping one of the outputs of the comparison logic circuits, a user can select the detection granularity.
摘要翻译：用于检测第一信号和第二信号之间的频移的频移检测电路包括串联耦合的两个或更多个延迟电路和两个或更多个比较逻辑电路。该系列中的第一个延迟电路接收第一和第二信号中的一个并产生延迟的副本。每个其他延迟电路接收由串联中的先前延迟电路产生的延迟复制品，并产生另一延迟复制品。因此，由每个延迟电路产生的信号从原始信号延迟不同的量。每个比较逻辑电路接收一个延迟的副本并且接收第一和第二信号中的另一个，即未被延迟电路接收的信号。作为响应，当比较逻辑电路检测到所述第一和第二信号中的另一个与延迟的副本之间的相位差时，产生频移检测信号。通过选择或敲击比较逻辑电路的输出之一，用户可以选择检测粒度。

2. 发明授权

US5977837A Phase selector for external frequency divider and phase locked loop 失效
标题翻译：外部分频器和锁相环的相位选择器
公开(公告)号：US5977837A
公开(公告)日：1999-11-02
申请号：US071447
申请日：1998-05-01
申请人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
发明人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
IPC分类号： G06F1/10 , H03L7/06 , H03L7/095 , H03K21/38 , H03L7/16
CPC分类号： G06F1/10 , H03L7/06 , H03L7/095 , Y10S331/02
摘要： A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.
摘要翻译：提供了一种从锁相环和相位选择器电路的反馈路径去除外部分频器和时钟形成电路的方法，用于使外部分频器与锁相环的参考时钟同步。参考时钟信号被施加到锁相环。锁相环的输出通过预定义的延迟耦合，并提供延迟的反馈时钟信号输入到锁相环。外部分频器位于预定义延迟外部的锁相环的输出端，并位于锁相环的反馈时钟信号路径之外。相位选择器电路识别参考时钟信号的正确相位并启动外部分频器。相位选择器电路包括边缘检测器，同步分配器和复位机。

3. 发明授权

US06289430B1 Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags 失效
标题翻译：在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置
公开(公告)号：US06289430B1
公开(公告)日：2001-09-11
申请号：US09251029
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1210
CPC分类号： G06F12/0875 , G06F12/0292
摘要： A method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation. A second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.
摘要翻译：提供了一种用于在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置。用于目标寻址和转换的装置包括耦合到处理器的处理器和第一地址转换单元。第一地址翻译单元将有效地址（EA）转换为实际地址（RA）。第一地址转换单元包括与每个地址转换相关联的目标标签。第二地址转换单元将实际地址（RA）转换为目标地址（TA）。第二地址转换单元包括与每个地址转换相关联的目标标签。高速缓存包括缓存目录，并且目标标签被存储到每个缓存填充的高速缓存目录中。

4. 发明授权

US06453366B1 Method and apparatus for direct memory access (DMA) with dataflow blocking for users 失效
标题翻译：用于直接存储器访问（DMA）的方法和装置，具有用户的数据流阻塞
公开(公告)号：US06453366B1
公开(公告)日：2002-09-17
申请号：US09251043
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.
摘要翻译：提供了一种用于实现具有用于处理通信系统中的数据通信的用户的数据流阻塞的直接存储器访问（DMA）的方法和装置。 DMA起始地址寄存器接收初始DMA起始地址，DMA长度寄存器接收初始DMA长度。 DMA状态机接收用于启动DMA的控制输入。 DMA状态机更新DMA起始地址以提供当前的DMA起始地址。 DMA状态机加载DMA结束地址。 DMA阻塞逻辑接收当前DMA起始地址和DMA结束地址，并仅在当前活动DMA区域内阻止接收到的存储器请求。

5. 发明授权

US06910201B2 Custom clock interconnects on a standardized silicon platform 失效
公开(公告)号：US06910201B2
公开(公告)日：2005-06-21
申请号：US10664137
申请日：2003-09-17
申请人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
发明人： Jonathan William Byrn , James Arnold Jensen , Matthew Scott Wingren
IPC分类号： G06F17/50 , H01L27/02 , H01L27/10 , H02H3/00
CPC分类号： G06F17/5045 , H01L27/0203
摘要： A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

6. 发明授权

US06823502B2 Placement of configurable input/output buffer structures during design of integrated circuits 失效
标题翻译：在集成电路设计期间配置输入/输出缓冲结构
公开(公告)号：US06823502B2
公开(公告)日：2004-11-23
申请号：US10334568
申请日：2002-12-31
申请人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
发明人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.
摘要翻译：考虑到产品的扩散可配置I / O块和/或I / O硬件的要求，用于设计集成电路和半导体产品的工具，为I / O缓冲结构生成正确的RTL。给定部分制造的半导体产品的切片描述，设计者可以生成应用集的I / O资源。然后给出具有晶体管结构以及扩散的可配置I / O块和/或I / O硬件以及多个伴随壳的应用组，这里的I / O生成工具自动读取具有切片描述的数据库和从晶体管结构生成I / O缓冲结构。 I / O生成工具进一步调整并集成了具有自己的逻辑的客户的两个或两个客户的输入，并且请求特定的半导体产品或者从它们的预先建立的逻辑获得IP核。 I / O生成工具可以从晶体管结构创建正确的RTL，以正确布局，定时，测试和半导体产品的I / O缓冲放大器的功能，无论是增量还是全局。一旦创建了I / O缓冲区结构，它们就被多个shell限定，包括验证shell，静态时序分析shell，制造测试shell和RTL分析shell。

7. 发明授权

US06765911B1 Communications adapter for implementing communications in a network and providing multiple modes of communications 失效
标题翻译：用于在网络中实现通信并提供多种通信模式的通信适配器
公开(公告)号：US06765911B1
公开(公告)日：2004-07-20
申请号：US09243858
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： H04L1256
CPC分类号： H04L47/58 , H04L12/5601 , H04L47/50 , H04L2012/5652 , H04L2012/5679
摘要： A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.
摘要翻译：提供了一种用于在通信网络中实现通信的方法和装置。用于实现通信的装置包括到通信网络的系统接口。调度器调度入队单元和要发送的入队帧。分段器将帧和小区划分成应用于媒体适配块的小区或帧，以在多个模式中选择的一个模式中进行传输。

8. 发明授权

US06498782B1 Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation 有权
标题翻译：通信方式和千兆以太网通信适配器提供服务质量和接收机连接速度差异化
公开(公告)号：US06498782B1
公开(公告)日：2002-12-24
申请号：US09243956
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： G06F1100
CPC分类号： H04L47/24 , H04L12/40032 , H04L12/4015 , H04L12/413 , H04L47/10 , H04L47/22 , H04L47/50 , H04L47/568 , H04L47/6215
摘要： A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.
摘要翻译：提供了一种用于实现通信网络中的通信的方法和千兆以太网通信适配器。定义要发送的数据的传输队列。为传输队列设置传输速率。要发送的数据在传输队列中排队。传输队列可以被划分为多个优先级队列，例如使用时轮，并为每个传输队列设置一个传输速率。

9. 发明授权

US06181705B2 System and method for management a communications buffer 失效
标题翻译：用于管理通信缓冲区的系统和方法
公开(公告)号：US06181705B2
公开(公告)日：2001-01-30
申请号：US08691803
申请日：1996-08-14
申请人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
发明人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
IPC分类号： H04L1308
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9052
摘要： A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.
摘要翻译：网络缓冲存储器被划分为包括多个小节连续部分和多个巨型图连续部分的位置池。可用于存储数据包的tinygram连续区段列在tinygram指针列表中。可用于存储数据包的巨型连续段也列在巨型指针列表中。用于将分组区分为微小图形和巨型图形的阈值被编程。当接收到数据包时，将根据阈值进行测量。响应于在到达阈值之前检测到分组状态的结束，将分组存储在微小的连续部分中。否则，数据包存储在巨型图连续部分。部分的可用性是通过查询指针的FIFO列表来确定的。

10. 发明授权

US5761716A Rate based memory replacement mechanism for replacing cache entries when the cache is full 失效
标题翻译：基于速率的内存替换机制，用于在缓存已满时替换缓存条目
公开(公告)号：US5761716A
公开(公告)日：1998-06-02
申请号：US640605
申请日：1996-05-01
申请人： Jonathan William Byrn , Gary Scott Delp , Kevin Gerard Plotz
发明人： Jonathan William Byrn , Gary Scott Delp , Kevin Gerard Plotz
IPC分类号： G06F12/12 , G06F13/00
CPC分类号： G06F12/121
摘要： A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.
摘要翻译：一种基于速率的机制，用于在高速缓存已满时确定要在高速缓存中替换的数据。计算机系统处理与多个通道或过程相关联的数据。这些通道或过程具有不同的循环速率。当缓存已满时，系统通过选择具有最低速率且最近使用的缓存中的数据块来选择要替换的数据。

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