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1. 发明授权

US5758087A Apparatus and method for predicted response generation 失效
标题翻译：用于预测响应生成的装置和方法
公开(公告)号：US5758087A
公开(公告)日：1998-05-26
申请号：US664131
申请日：1996-06-14
申请人： Kenneth Dale Aaker , Gary Scott Delp , Brad Louis Brech
发明人： Kenneth Dale Aaker , Gary Scott Delp , Brad Louis Brech
IPC分类号： G06F13/00 , G06F9/46 , G06F12/00 , G06F17/30 , H04L29/06 , G06F9/06
CPC分类号： H04L67/42
摘要： A method and apparatus are provided for generation of predicted responses in a computer communications network system. A server in the computer communications network system predicts the client's next request based on the present client's request. The server sets a trigger that recognizes a match of the client's predicted request. When a client's predicted request arrives, the trigger sends the response. Additionally, the server associates a timeout action with the predicted response so that if a predicted request is not received within the timeout interval or other events occur before the predicted request arrives, the triggered response is removed and an alternative action is performed.
摘要翻译：提供了一种用于在计算机通信网络系统中产生预测响应的方法和装置。计算机通信网络系统中的服务器基于当前客户端的请求预测客户端的下一个请求。服务器设置一个触发器，用于识别客户端预测请求的匹配。当客户端的预测请求到达时，触发器发送响应。另外，服务器将超时动作与预测的响应相关联，使得如果在超时间隔内未接收到预测请求或在预测请求到达之前发生其他事件，则触发的响应被移除，并执行替代动作。

2. 发明授权

US5953535A Using intelligent bus bridges with pico-code to service interrupts and improve interrupt response 失效
标题翻译：使用带微微码的智能总线桥服务中断并改善中断响应
公开(公告)号：US5953535A
公开(公告)日：1999-09-14
申请号：US826032
申请日：1997-03-28
申请人： Brad Louis Brech
发明人： Brad Louis Brech
IPC分类号： G06F13/24 , G06F9/46 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4027
摘要： A computer system having an improved method of handling interrupts associated with I/O operations to reduce interrupt latencies. The computer system includes one or more processing units, a memory device (e.g., RAM) connected to the processing unit via a system bus, and a plurality of I/O devices providing interrupt sources, connected to the processor via an I/O bus and a bus bridge. The bus bridge has incorporated therein or connected thereto means for intercepting interrupt requests transmitted to the processing unit and handling the interrupt requests without suspending the current process in the processing unit. In the preferred embodiment, the means for intercepting and handling the interrupts includes a storage device or array having pico-code instructions which are scheduled for execution in a sequencer by the interrupt control logic. If the pico-code sees an interrupt that it is not programmed to handle (such as an exception), it can pass that interrupt to the appropriate processing unit for handling. Additional bus bridges having pico-code instructions can be provided for multi-bus systems having additional interrupt sources connected via other busses.
摘要翻译：一种具有处理与I / O操作相关联的中断的改进方法以减少中断延迟的计算机系统。计算机系统包括一个或多个处理单元，经由系统总线连接到处理单元的存储器件（例如，RAM）以及提供中断源的多个I / O设备，经由I / O总线连接到处理器和一座公共汽车桥。总线桥已经并入其中或与其连接，用于拦截发送到处理单元的中断请求并处理中断请求而不将当前进程挂起在处理单元中。在优选实施例中，用于截取和处理中断的装置包括具有微调码指令的存储装置或阵列，其被安排为由中断控制逻辑在定序器中执行。如果微微代码看到一个未被编程处理的中断（例如异常），则可以将该中断传递给适当的处理单元进行处理。可以为具有通过其它总线连接的附加中断源的多总线系统提供具有微码指令的附加总线桥。

3. 发明授权

US5790887A Method and apparatus for processing programmed input/output (PIO) operations in a computer system 失效
标题翻译：用于在计算机系统中处理编程输入/输出（PIO）操作的方法和装置
公开(公告)号：US5790887A
公开(公告)日：1998-08-04
申请号：US601681
申请日：1996-02-15
申请人： Brad Louis Brech
发明人： Brad Louis Brech
IPC分类号： G06F13/12 , G06F9/28
CPC分类号： G06F13/126
摘要： A method and apparatus are provided for processing programmed input/output (PIO) operations in a computer system. A batched list of PIO operations is stored in a buffer. Then the batched list of PIO operations is moved as a single system bus operation to an I/O bus interface unit. The I/O bus interface unit includes sequencer logic. The sequencer logic is used for executing the batched list of PIO operations and for providing an ordered sequence of PIO operations to a system I/O bus. The method and apparatus of the invention enhances the use of non-intelligent I/O adapters in a computer system by reducing the overhead of system PIO operations. Also the correctly ordered sequence of PIO commands provided by the sequencer logic facilitates the use of non-intelligent I/O adapters in reduced instruction-set computer (RISC) systems.
摘要翻译：提供了一种用于在计算机系统中处理编程输入/输出（PIO）操作的方法和装置。 PIO操作的批量列表存储在缓冲区中。然后将批量列表的PIO操作作为单个系统总线操作移动到I / O总线接口单元。 I / O总线接口单元包括定序器逻辑。定序器逻辑用于执行PIO操作的批量列表，并向系统I / O总线提供PIO操作的有序序列。本发明的方法和装置通过减少系统PIO操作的开销来增强计算机系统中非智能I / O适配器的使用。此外，定序器逻辑提供的正确排序的PIO命令序列有助于在精简指令集计算机（RISC）系统中使用非智能I / O适配器。

4. 发明授权

US5754768A System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions 失效
标题翻译：系统用于在不存在异常情况时，对来自不同会话的数据包进行选择性和累积分组，并在预选的时间条件之后发送数据包
公开(公告)号：US5754768A
公开(公告)日：1998-05-19
申请号：US685126
申请日：1996-07-23
申请人： Brad Louis Brech , Gary Scott Delp , Albert Alfonse Slane
发明人： Brad Louis Brech , Gary Scott Delp , Albert Alfonse Slane
IPC分类号： H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： H04L29/06 , H04L69/22 , H04L69/32
摘要： A method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system are disclosed. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.
摘要翻译：公开了一种用于增强在数据处理系统内的逻辑单元处接收的多个相关分组的处理的方法和装置处理系统。在逻辑单元处接收多个分组。然后检查多个分组中的每一个，并且为多个分组中的每个分组获得会话标识。在预选时间窗口期间，多个分组中的每一个与组相关联。组中的每个分组具有与组内的每个其他分组相同的会话标识。

5. 发明授权

US06181705B2 System and method for management a communications buffer 失效
标题翻译：用于管理通信缓冲区的系统和方法
公开(公告)号：US06181705B2
公开(公告)日：2001-01-30
申请号：US08691803
申请日：1996-08-14
申请人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
发明人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
IPC分类号： H04L1308
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9052
摘要： A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.
摘要翻译：网络缓冲存储器被划分为包括多个小节连续部分和多个巨型图连续部分的位置池。可用于存储数据包的tinygram连续区段列在tinygram指针列表中。可用于存储数据包的巨型连续段也列在巨型指针列表中。用于将分组区分为微小图形和巨型图形的阈值被编程。当接收到数据包时，将根据阈值进行测量。响应于在到达阈值之前检测到分组状态的结束，将分组存储在微小的连续部分中。否则，数据包存储在巨型图连续部分。部分的可用性是通过查询指针的FIFO列表来确定的。

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