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1. 发明授权

US06289430B1 Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags 失效
标题翻译：在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置
公开(公告)号：US06289430B1
公开(公告)日：2001-09-11
申请号：US09251029
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1210
CPC分类号： G06F12/0875 , G06F12/0292
摘要： A method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation. A second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.
摘要翻译：提供了一种用于在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置。用于目标寻址和转换的装置包括耦合到处理器的处理器和第一地址转换单元。第一地址翻译单元将有效地址（EA）转换为实际地址（RA）。第一地址转换单元包括与每个地址转换相关联的目标标签。第二地址转换单元将实际地址（RA）转换为目标地址（TA）。第二地址转换单元包括与每个地址转换相关联的目标标签。高速缓存包括缓存目录，并且目标标签被存储到每个缓存填充的高速缓存目录中。

2. 发明授权

US06453366B1 Method and apparatus for direct memory access (DMA) with dataflow blocking for users 失效
标题翻译：用于直接存储器访问（DMA）的方法和装置，具有用户的数据流阻塞
公开(公告)号：US06453366B1
公开(公告)日：2002-09-17
申请号：US09251043
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.
摘要翻译：提供了一种用于实现具有用于处理通信系统中的数据通信的用户的数据流阻塞的直接存储器访问（DMA）的方法和装置。 DMA起始地址寄存器接收初始DMA起始地址，DMA长度寄存器接收初始DMA长度。 DMA状态机接收用于启动DMA的控制输入。 DMA状态机更新DMA起始地址以提供当前的DMA起始地址。 DMA状态机加载DMA结束地址。 DMA阻塞逻辑接收当前DMA起始地址和DMA结束地址，并仅在当前活动DMA区域内阻止接收到的存储器请求。

3. 发明授权

US6011412A Frequency shift detection circuit with selectable granularity 失效
标题翻译：具有可选粒度的频移检测电路
公开(公告)号：US6011412A
公开(公告)日：2000-01-04
申请号：US70925
申请日：1998-05-01
申请人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
发明人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
IPC分类号： H03D13/00
CPC分类号： H03D13/004
摘要： A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica. By selecting or tapping one of the outputs of the comparison logic circuits, a user can select the detection granularity.
摘要翻译：用于检测第一信号和第二信号之间的频移的频移检测电路包括串联耦合的两个或更多个延迟电路和两个或更多个比较逻辑电路。该系列中的第一个延迟电路接收第一和第二信号中的一个并产生延迟的副本。每个其他延迟电路接收由串联中的先前延迟电路产生的延迟复制品，并产生另一延迟复制品。因此，由每个延迟电路产生的信号从原始信号延迟不同的量。每个比较逻辑电路接收一个延迟的副本并且接收第一和第二信号中的另一个，即未被延迟电路接收的信号。作为响应，当比较逻辑电路检测到所述第一和第二信号中的另一个与延迟的副本之间的相位差时，产生频移检测信号。通过选择或敲击比较逻辑电路的输出之一，用户可以选择检测粒度。

4. 发明授权

US5977837A Phase selector for external frequency divider and phase locked loop 失效
标题翻译：外部分频器和锁相环的相位选择器
公开(公告)号：US5977837A
公开(公告)日：1999-11-02
申请号：US071447
申请日：1998-05-01
申请人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
发明人： Jonathan William Byrn , Chad B. McBride , Brian Andrew Schuelke
IPC分类号： G06F1/10 , H03L7/06 , H03L7/095 , H03K21/38 , H03L7/16
CPC分类号： G06F1/10 , H03L7/06 , H03L7/095 , Y10S331/02
摘要： A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.
摘要翻译：提供了一种从锁相环和相位选择器电路的反馈路径去除外部分频器和时钟形成电路的方法，用于使外部分频器与锁相环的参考时钟同步。参考时钟信号被施加到锁相环。锁相环的输出通过预定义的延迟耦合，并提供延迟的反馈时钟信号输入到锁相环。外部分频器位于预定义延迟外部的锁相环的输出端，并位于锁相环的反馈时钟信号路径之外。相位选择器电路识别参考时钟信号的正确相位并启动外部分频器。相位选择器电路包括边缘检测器，同步分配器和复位机。

5. 发明授权

US07539840B2 Handling concurrent address translation cache misses and hits under those misses while maintaining command order 失效
标题翻译：在维护命令顺序的同时，处理并发地址转换高速缓存未命中和命中
公开(公告)号：US07539840B2
公开(公告)日：2009-05-26
申请号：US11420884
申请日：2006-05-30
申请人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
摘要翻译：一种方法处理并发地址转换高速缓存未命中并在这些未命中的命中，同时维持基于虚拟通道的命令顺序。命令存储在维护命令排序的命令处理单元中。将命令缓冲器索引分配给从命令处理单元发送到地址转换单元的每个地址。当发生地址转换高速缓存未命中时，发送存储器提取请求。 CBI被传回给具有信号的命令处理单元，以指示提取请求已经完成。命令处理单元使用CBI将要重新发布的命令和地址定位到地址转换单元。

6. 发明申请

US20090113134A1 Method and Cache Control Circuit for Replacing Cache Lines Using Alternate PLRU Algorithm and Victim Cache Coherency State 失效
标题翻译：使用替代PLRU算法和受害者缓存一致性状态替换缓存行的方法和缓存控制电路
公开(公告)号：US20090113134A1
公开(公告)日：2009-04-30
申请号：US11924163
申请日：2007-10-25
申请人： John David Irish , Chad B. McBride , Jack Chris Randolph
发明人： John David Irish , Chad B. McBride , Jack Chris Randolph
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F12/128
摘要： A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
摘要翻译：一种用于使用具有受害者高速缓存一致性状态的替代伪最近最少使用（PLRU）算法来替换高速缓存行的方法和高速缓存控制电路，以及设置有对象高速缓存控制电路所在的设计结构。当识别到同余类中的替换要求时，计算用于替换的第一PLRU高速缓存行和用于替换的替代PLRU高速缓存行。当用于替换的第一PLRU高速缓存行处于受害者高速缓存一致性状态时，替代的PLRU高速缓存行被选择使用。

7. 发明申请

US20080189501A1 Methods and Apparatus for Issuing Commands on a Bus 审中-公开
标题翻译：在公共汽车上发出命令的方法和装置
公开(公告)号：US20080189501A1
公开(公告)日：2008-08-07
申请号：US11671117
申请日：2007-02-05
申请人： John D. Irish , Chad B. McBride
发明人： John D. Irish , Chad B. McBride
IPC分类号： G06F12/00
CPC分类号： G06F13/1631
摘要： In a first aspect, a first method of issuing a command on a bus of a system is provided. The first method includes the steps of (1) receiving a first functional memory command in the system; (2) receiving a command to force the system to execute functional memory commands in order; (3) receiving a second functional memory command in the system; and (4) employing a dependency matrix to indicate the second functional memory command requires access to a same address as the first functional memory command whether or not the second functional memory command actually has an ordering dependency on the first functional memory command. The dependency matrix is adapted to store data indicating whether a functional memory command received by the system has an ordering dependency on one or more functional memory commands previously received by the system. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在系统总线上发出命令的方法。第一种方法包括以下步骤：（1）在系统中接收第一功能存储器命令; （2）接收强制系统依次执行功能存储器命令的命令; （3）在系统中接收第二功能存储器命令; 和（4）使用依赖矩阵来指示第二功能存储器命令需要访问与第一功能存储器命令相同的地址，无论第二功能存储器命令是否实际上具有对第一功能存储器命令的排序依赖性。依赖矩阵适于存储指示系统接收的功能存储器命令是否具有与先前由系统接收的一个或多个功能存储器命令的排序依赖关系的数据。提供了许多其他方面。

8. 发明申请

US20080126641A1 Methods and Apparatus for Combining Commands Prior to Issuing the Commands on a Bus 审中-公开
标题翻译：在总线上发布命令之前组合命令的方法和装置
公开(公告)号：US20080126641A1
公开(公告)日：2008-05-29
申请号：US11468889
申请日：2006-08-31
申请人： John D. Irish , Chad B. McBride
发明人： John D. Irish , Chad B. McBride
IPC分类号： G06F13/00
CPC分类号： G06F13/1631
摘要： In a first aspect, a first method of issuing a command on a bus is provided. The first method includes the steps of (1) receiving a first command associated with a first address; (2) delaying the issue of the first command on the bus for a time period; (3) if a second command associated with a second address contiguous with the first address is not received before the time period elapses, issuing the first command on the bus after the time period elapses; and (4) if the second command associated with the second address contiguous with the first address is received before the first command is issued on the bus, combining the first and second commands into a combined command associated with the first address. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在总线上发出命令的方法。第一种方法包括以下步骤：（1）接收与第一地址相关联的第一命令; （二）延迟公交一期时间的问题; （3）如果在经过时间段之前没有接收到与第一地址相邻的第二地址相关联的第二命令，则在经过该时间段之后在总线上发出第一命令; 和（4）如果在总线上发出第一命令之前接收到与第一地址相邻的第二地址相关联的第二命令，则将第一和第二命令组合成与第一地址相关联的组合命令。提供了许多其他方面。

9. 发明授权

US09146835B2 Methods and systems with delayed execution of multiple processors 有权
标题翻译：延迟执行多个处理器的方法和系统
公开(公告)号：US09146835B2
公开(公告)日：2015-09-29
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F11/36 , G06F11/16
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

10. 发明申请

US20130179720A1 MULTIPLE PROCESSOR DELAYED EXECUTION 有权
标题翻译：多处理器延迟执行
公开(公告)号：US20130179720A1
公开(公告)日：2013-07-11
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

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