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1. 发明申请

US20140132320A1 LOSS OF LOCK DETECTOR FOR CLOCK AND DATA RECOVERY SYSTEM 有权
标题翻译：用于时钟和数据恢复系统的锁定检测器丢失
公开(公告)号：US20140132320A1
公开(公告)日：2014-05-15
申请号：US13675520
申请日：2012-11-13
申请人： LSI CORPORATION
发明人： Vladimir Sindalovsky , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H03L7/087
CPC分类号： H03L7/087 , H03L7/0807 , H03L7/095 , H04L7/0083 , H04L7/033 , Y10S331/02
摘要： An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.
摘要翻译：一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平第一率。可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。

2. 发明申请

US20120105117A1 Phase-Lock Loop 有权
标题翻译：锁相环
公开(公告)号：US20120105117A1
公开(公告)日：2012-05-03
申请号：US13347586
申请日：2012-01-10
申请人： Chin Yeong Koh , Kar Ming Yong
发明人： Chin Yeong Koh , Kar Ming Yong
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0995 , H03L7/113 , H03L7/18 , Y10S331/02
摘要： A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.
摘要翻译：与常规技术相比，锁相环具有减少的锁定时间。锁相环路将其输出信号与参考信号进行比较，并响应于此而改变控制信号，使得输出信号可以具有期望的频率。

3. 发明授权

US08076979B2 Lock detection circuit for phase locked loop 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US08076979B2
公开(公告)日：2011-12-13
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03J7/04 , H03L7/02
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

4. 发明申请

US20110215873A1 NOVEL SWITCHED PHASE AND FREQUENCY DETECTOR BASED DPLL CIRCUIT WITH EXCELLENT WANDER AND JITTER PERFORMANCE AND FAST FREQUENCY ACQUISITION 有权
标题翻译：基于新型开关相位和频率检测器的DPLL电路，具有优异的宽带和抖动性能和快速采集
公开(公告)号：US20110215873A1
公开(公告)日：2011-09-08
申请号：US12715749
申请日：2010-03-02
申请人： Leo Montreuil , Larry Stephen McKinney , Jiening Ao , Joel Paul Jenkins
发明人： Leo Montreuil , Larry Stephen McKinney , Jiening Ao , Joel Paul Jenkins
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , Y10S331/02
摘要： Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.
摘要翻译：本发明的一些实施例可以包括包括固件的DPLL电路。固件可以包括能够接收参考时钟定时信号和VCXO时钟定时信号的重新采样的NCO相位检测器。重新采样的NCO相位检测器可以包括能够接收相位输出和VCXO时钟定时信号并重新采样相位输出的重采样器; 以及减法器，其能够从所计算的相位输出的平均值接收所述重采样相位输出并减去所述重采样相位输出。固件还可以包括能够接收参考时钟定时信号和VCXO时钟定时信号的频率检测器; 以及能够根据频率锁定状态在重新采样的NCO相位检测器和频率检测器之间切换的多路复用器。

5. 发明授权

US07719368B1 Configurable reset circuit for a phase-locked loop 有权
标题翻译：用于锁相环的可配置复位电路
公开(公告)号：US07719368B1
公开(公告)日：2010-05-18
申请号：US12273913
申请日：2008-11-19
申请人： Paul Jeffrey Smith , Travis A. Bradfield , Jeffrey K. Whitt
发明人： Paul Jeffrey Smith , Travis A. Bradfield , Jeffrey K. Whitt
IPC分类号： H03L7/095
CPC分类号： H03L7/10 , H03L7/105 , Y10S331/02
摘要： A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.
摘要翻译：消除PLL中的失控状况的方法包括以下步骤：确定PLL是否被锁定到输入参考信号; 当PLL未被锁定到输入参考信号时，确定由PLL产生的输出信号的频率是否超过规定的最大频率; 并且当PLL产生的输出信号的频率超过规定的最大频率时，复位PLL从而消除失控状况。

6. 发明授权

US07698590B2 Method and apparatus for timing and event processing in wireless systems 有权
标题翻译：无线系统中定时和事件处理的方法和装置
公开(公告)号：US07698590B2
公开(公告)日：2010-04-13
申请号：US11985374
申请日：2007-11-15
申请人： Poul R. Jensen , Thorkild Leth Moller, legal representative , Morten Nielsen , Mogens Christiansen
发明人： Poul R. Jensen , Morten Nielsen , Mogens Christiansen
IPC分类号： G06F1/14
CPC分类号： G06F11/3636 , G06F1/04 , G06F1/08 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3836 , G06F9/3851 , G06F9/3869 , G06F9/4843 , G06F12/0842 , G06F12/0859 , G06F13/28 , G06F13/385 , G06F2213/3814 , H03L7/0802 , H03L7/095 , H03L7/183 , H04W88/06 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/171 , Y02D10/172 , Y02D10/24 , Y02D50/20 , Y02D70/1222 , Y02D70/124 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y10S331/02
摘要： A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.
摘要翻译：提供数字基带处理器用于与不同的无线系统并发操作。数字基带处理器包括用于执行数字信号处理器指令的数字信号处理器，用于执行微控制器指令的微控制器，以及由数字信号处理器和微控制器控制的定时和事件处理器，用于执行时序敏感指令。定时和事件处理器包括用于执行时间敏感指令线程的多个指令定序器和用于产生用于启动多个指令定序器中的每一个上的指令线程的执行的定时信号的时基发生器。

7. 发明申请

US20090251226A1 LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP 有权
标题翻译：锁相环锁定检测电路
公开(公告)号：US20090251226A1
公开(公告)日：2009-10-08
申请号：US12416933
申请日：2009-04-02
申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
发明人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
摘要翻译：用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器的反馈信号的多个时钟周期。异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。

8. 发明授权

US07388441B2 Robust phase-lock detector 有权
标题翻译：强大的锁相检测器
公开(公告)号：US07388441B2
公开(公告)日：2008-06-17
申请号：US11439724
申请日：2006-05-23
申请人： Donald J. Delzer
发明人： Donald J. Delzer
IPC分类号： H03L7/95
CPC分类号： H03L7/095 , H03L7/085 , Y10S331/02
摘要： A robust phase-lock detector for a phase-locked loop examines both the sum frequency and baseband components of an error signal from the phase-locked loop to determine that both a reference signal and an output signal for the phase-locked loop are present and that the reference and output signals have a desired phase relationship. An IF detector selects the sum frequency component, which is the sum of the reference frequency and a subdivided frequency from the output signal, and detects its presence. A baseband detector selects the baseband component and detects whether the baseband component is approximately zero volts. The outputs from the IF detector and the baseband detector are combined to produce a lock signal, indicating that the phase-locked loop is locked, i.e., the reference and output signals are present and have the desired phase relationship with respect to each other.
摘要翻译：用于锁相环的鲁棒锁相检测器检测来自锁相环的误差信号的和频和基带分量，以确定参考信号和锁相环的输出信号都存在，参考和输出信号具有期望的相位关系。 IF检测器选择和频率分量，该频率分量是来自输出信号的参考频率和细分频率之和，并检测其存在。基带检测器选择基带分量并检测基带分量是否近似为零伏特。来自IF检测器和基带检测器的输出被组合以产生锁定信号，指示锁相环被锁定，即参考和输出信号存在并且具有相对于彼此的期望的相位关系。

9. 发明授权

US07323946B2 Lock detect circuit for a phase locked loop 有权
标题翻译：用于锁相环路的锁定检测电路
公开(公告)号：US07323946B2
公开(公告)日：2008-01-29
申请号：US11254569
申请日：2005-10-20
申请人： James D. Seefeldt , Bradley A. Kantor
发明人： James D. Seefeldt , Bradley A. Kantor
IPC分类号： H03L7/085 , H03L7/08
CPC分类号： H03D13/004 , H03L7/095 , Y10S331/02
摘要： An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.
摘要翻译：描述了用于确定锁相环（PLL）的锁定状态的改进的系统和方法。锁定检测电路产生快速锁定检测信号，其可用于检测瞬时的锁定损失。锁定检测电路还可以包括相位对准检测电路，用于检测参考时钟和反馈时钟的相位中的未对准。此外，锁定检测电路可以包括参考时钟检测电路，以检测是否检测到参考时钟信号。来自所有上述电路的输出信号可以被传送到逻辑电路，以便产生增强的锁定检测信号。扩展锁定检测信号也可以被传送到逻辑电路。

10. 发明授权

US07323940B2 Adaptive cycle-slipped detector for unlock detection in phase-locked loop applications 有权
标题翻译：自适应循环滑动检测器，用于锁相环应用中的解锁检测
公开(公告)号：US07323940B2
公开(公告)日：2008-01-29
申请号：US11365578
申请日：2006-02-28
申请人： Wing J. Mar , Sebastien Louveaux , Wim Cresens
发明人： Wing J. Mar , Sebastien Louveaux , Wim Cresens
IPC分类号： H03L7/085 , H03L7/095
CPC分类号： H03L7/095 , H03L7/18 , Y10S331/02
摘要： An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit. The ACSD may include a phase comparator, a phase shifter in signal communication with the phase comparator, and a cycle-slipped detector (“CSD”) in signal communication with the phase shifter.
摘要翻译：用于锁相环（“PLL”）电路的自适应周期滑动检测器（“ACSD”）。 ACSD可以包括相位比较器，与相位比较器进行信号通信的移相器，以及与移相器进行信号通信的周期滑动检测器（“CSD”）。

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